Changeset 122 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit
- Timestamp:
- Jun 3, 2009, 10:15:51 AM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit
- Files:
-
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h
r118 r122 85 85 public : SC_IN (Ttype_t ) * in_EXECUTE_IN_TYPE ; 86 86 public : SC_IN (Tlsq_ptr_t ) * in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE; 87 public : SC_IN (Tlsq_ptr_t ) * in_EXECUTE_IN_STORE_QUEUE_PTR_READ ; 88 public : SC_IN (Tcontrol_t ) * in_EXECUTE_IN_STORE_QUEUE_EMPTY ; 87 89 public : SC_IN (Tlsq_ptr_t ) * in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE; 88 90 public : SC_IN (Tcontrol_t ) * in_EXECUTE_IN_HAS_IMMEDIAT ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp
r118 r122 63 63 ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_TYPE ,"type" ,Ttype_t , _param->_size_type ); 64 64 ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); 65 ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t ,_param->_size_store_queue_ptr); 66 ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_STORE_QUEUE_EMPTY ,"store_queue_empty" ,Tcontrol_t , 1); 65 67 ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr); 66 68 ALLOC0_SIGNAL_IN ( in_EXECUTE_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t , 1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp
r118 r122 39 39 DELETE0_SIGNAL( in_EXECUTE_IN_TYPE , _param->_size_type ); 40 40 DELETE0_SIGNAL( in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE ,_param->_size_store_queue_ptr); 41 DELETE0_SIGNAL( in_EXECUTE_IN_STORE_QUEUE_PTR_READ ,_param->_size_store_queue_ptr); 42 DELETE0_SIGNAL( in_EXECUTE_IN_STORE_QUEUE_EMPTY , 1); 41 43 DELETE0_SIGNAL( in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE ,_param->_size_load_queue_ptr); 42 44 DELETE0_SIGNAL( in_EXECUTE_IN_HAS_IMMEDIAT , 1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r117 r122 103 103 public : SC_IN (Ttype_t ) ** in_MEMORY_IN_TYPE ;//[nb_inst_memory] 104 104 public : SC_IN (Tlsq_ptr_t ) ** in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;//[nb_inst_memory] 105 public : SC_IN (Tlsq_ptr_t ) ** in_MEMORY_IN_STORE_QUEUE_PTR_READ ;//[nb_inst_memory] 106 public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_STORE_QUEUE_EMPTY ;//[nb_inst_memory] 105 107 public : SC_IN (Tlsq_ptr_t ) ** in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_memory] 106 108 public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_HAS_IMMEDIAT ;//[nb_inst_memory] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
r119 r122 73 73 //public : Tgeneral_address_t _num_reg_rd ; 74 74 public : Texception_t _exception ; 75 public : bool _send_commit ; 75 76 76 77 friend std::ostream & operator << (std::ostream& os, const Tstore_queue_entry_t & x) … … 112 113 public : Tlsq_ptr_t _load_queue_ptr_write ; 113 114 public : Tlsq_ptr_t _store_queue_ptr_write; 115 public : Tlsq_ptr_t _store_queue_ptr_read ; 116 public : Tcontrol_t _store_queue_empty ; 114 117 public : Tdcache_address_t _address ; 115 118 public : Tcontrol_t _write_rd ; … … 123 126 << " * context, front_end, ooo_engine_id : " << toString(x._context_id) << " - " << toString(x._front_end_id) << " - " << toString(x._ooo_engine_id) << std::endl 124 127 << " * operation : " << toString(x._operation) << std::endl 125 << " * load, store ptr_ write : " << toString(x._load_queue_ptr_write) << " - " << toString(x._store_queue_ptr_write) << std::endl128 << " * load, store ptr_(write/read) empty: " << toString(x._load_queue_ptr_write) << " - " << toString(x._store_queue_ptr_write) << " - " << toString(x._store_queue_ptr_read) << " - " << toString(x._store_queue_empty) << std::endl 126 129 << " * exception : " << toString(x._exception) << std::endl 127 130 << std::hex … … 166 169 public : Toperation_t _operation ; 167 170 public : Tlsq_ptr_t _store_queue_ptr_write; 171 public : Tlsq_ptr_t _store_queue_ptr_read ; 172 public : Tcontrol_t _store_queue_empty ; 168 173 public : Tdcache_address_t _address ; 169 174 public : Tdcache_address_t _check_hit_byte ; … … 183 188 << " * context, front_end, ooo_engine_id : " << toString(x._context_id) << " - " << toString(x._front_end_id) << " - " << toString(x._ooo_engine_id) << std::endl 184 189 << " * operation : " << toString(x._operation) << std::endl 185 << " * store_queue _ptr_write : " << toString(x._store_queue_ptr_write) <<std::endl190 << " * store_queue ptr_(write,read) empty: " << toString(x._store_queue_ptr_write) << " - " << toString(x._store_queue_ptr_read) << " - " << toString(x._store_queue_empty) <<std::endl 186 191 << " * exception : " << toString(x._exception) << std::endl 187 192 << " * check_hit, check_hit_byte : " << toString(x._check_hit) << " - " << toString(x._check_hit_byte) << std::endl -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
r117 r122 65 65 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 66 66 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 67 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 68 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_EMPTY ,"store_queue_empty" ,Tcontrol_t ,1); 67 69 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 68 70 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
r117 r122 45 45 DELETE1_SIGNAL( in_MEMORY_IN_TYPE ,_param->_nb_inst_memory,_param->_size_type ); 46 46 DELETE1_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory,_param->_size_store_queue_ptr ); 47 DELETE1_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_READ ,_param->_nb_inst_memory,_param->_size_store_queue_ptr ); 48 DELETE1_SIGNAL( in_MEMORY_IN_STORE_QUEUE_EMPTY ,_param->_nb_inst_memory,1); 47 49 DELETE1_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory,_param->_size_load_queue_ptr ); 48 50 DELETE1_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory,1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
r117 r122 39 39 // Tspecial_address_t memory_out_num_reg_re = 0; 40 40 // Tspecial_data_t memory_out_data_re = 0; 41 Tcontrol_t memory_out_no_sequence = 0; 41 42 Texception_t memory_out_exception = 0; 42 43 … … 98 99 { 99 100 log_printf(TRACE,Load_store_unit,FUNCTION," * Store queue"); 100 // Can retire an store instruction if : 101 // * state is commit 102 // * none load must check this store 103 if ((_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) and 104 (reg_STORE_QUEUE_NB_CHECK [reg_STORE_QUEUE_PTR_READ] == 0)) 105 { 106 log_printf(TRACE,Load_store_unit,FUNCTION," * find : %d",reg_STORE_QUEUE_PTR_READ); 107 108 internal_MEMORY_OUT_VAL = 1; 109 internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE; 110 111 memory_out_context_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id; 112 memory_out_front_end_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id; 113 memory_out_ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id; 114 memory_out_packet_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._packet_id ; 115 // memory_out_write_rd 116 // memory_out_num_reg_rd 117 memory_out_data_rd = _store_queue [reg_STORE_QUEUE_PTR_READ]._address; // to the exception 118 memory_out_exception = _store_queue [reg_STORE_QUEUE_PTR_READ]._exception; 119 } 120 } 101 102 for (uint32_t i=0; i<_param->_size_store_queue; ++i) 103 { 104 internal_MEMORY_OUT_PTR = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; 105 // Can retire an store instruction if : 106 // * state is commit 107 // * none load must check this store 108 109 110 bool val_head = ((i==0) and 111 (_store_queue [internal_MEMORY_OUT_PTR]._state == STORE_QUEUE_COMMIT) and 112 (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == true) and 113 (reg_STORE_QUEUE_NB_CHECK [internal_MEMORY_OUT_PTR] == 0) 114 ); 115 116 bool val_commit = ((_store_queue [internal_MEMORY_OUT_PTR]._state != STORE_QUEUE_EMPTY) and 117 (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == false)); 118 119 if (val_head or val_commit) 120 { 121 log_printf(TRACE,Load_store_unit,FUNCTION," * find : %d",internal_MEMORY_OUT_PTR); 122 123 internal_MEMORY_OUT_VAL = 1; 124 internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE; 125 126 memory_out_context_id = _store_queue [internal_MEMORY_OUT_PTR]._context_id; 127 memory_out_front_end_id = _store_queue [internal_MEMORY_OUT_PTR]._front_end_id; 128 memory_out_ooo_engine_id = _store_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id; 129 memory_out_packet_id = _store_queue [internal_MEMORY_OUT_PTR]._packet_id ; 130 // memory_out_write_rd 131 // memory_out_num_reg_rd 132 memory_out_data_rd = _store_queue [internal_MEMORY_OUT_PTR]._address; // to the exception 133 memory_out_exception = _store_queue [internal_MEMORY_OUT_PTR]._exception; 134 memory_out_no_sequence = val_commit; 135 break; // find an entry 136 } 137 138 } 139 } 140 121 141 // write output 122 142 PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL); … … 142 162 PORT_WRITE(out_MEMORY_OUT_DATA_RE [0], 0); 143 163 PORT_WRITE(out_MEMORY_OUT_EXCEPTION [0], memory_out_exception ); 144 PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE [0], 0); 164 PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE [0], memory_out_no_sequence );// hack 165 #ifdef DEBUG 166 PORT_WRITE(out_MEMORY_OUT_ADDRESS [0], memory_out_data_rd); 167 #else 145 168 PORT_WRITE(out_MEMORY_OUT_ADDRESS [0], 0); 169 #endif 146 170 147 171 // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r119 r122 275 275 // ======================= 276 276 277 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]", reg_STORE_QUEUE_PTR_READ);277 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",internal_MEMORY_OUT_PTR); 278 278 279 279 // Entry flush and increase the read pointer 280 _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY; 281 282 reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue; 280 if (_store_queue [internal_MEMORY_OUT_PTR]._send_commit) 281 { 282 _store_queue [internal_MEMORY_OUT_PTR]._state = STORE_QUEUE_EMPTY; 283 reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue; 284 } 285 else 286 _store_queue [internal_MEMORY_OUT_PTR]._send_commit = true; 283 287 284 288 break; … … 339 343 { 340 344 // Get an index from load queue 341 uint32_t index_load = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue;345 uint32_t index_load_queue = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue; 342 346 343 347 // Test if this load must ckecked store queue 344 if (((_load_queue[index_load ]._state == LOAD_QUEUE_WAIT_CHECK) or345 (_load_queue[index_load ]._state == LOAD_QUEUE_COMMIT_CHECK) or346 (_load_queue[index_load ]._state == LOAD_QUEUE_CHECK)) and347 is_operation_memory_load(_load_queue[index_load ]._operation))348 if (((_load_queue[index_load_queue]._state == LOAD_QUEUE_WAIT_CHECK) or 349 (_load_queue[index_load_queue]._state == LOAD_QUEUE_COMMIT_CHECK) or 350 (_load_queue[index_load_queue]._state == LOAD_QUEUE_CHECK)) and 351 is_operation_memory_load(_load_queue[index_load_queue]._operation)) 348 352 { 349 log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load );353 log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load_queue); 350 354 351 355 nb_check++; // use one port 352 356 353 357 // find a entry that it need a check 354 Tlsq_ptr_t index_store = _load_queue[index_load]._store_queue_ptr_write; 355 // Tlsq_ptr_t index_store_old = index_store; 358 Tlsq_ptr_t store_queue_ptr_write = _load_queue[index_load_queue]._store_queue_ptr_write; 359 Tlsq_ptr_t store_queue_ptr_read = _load_queue[index_load_queue]._store_queue_ptr_read ; 360 Tlsq_ptr_t store_queue_empty = _load_queue[index_load_queue]._store_queue_empty ; 361 // Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write; 356 362 357 363 // Init variable … … 365 371 // * when a store is out of store queue, also it was in head of re order buffer. Also, they are none previous load. 366 372 367 log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store); 368 log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ); 369 370 if (index_store == reg_STORE_QUEUE_PTR_READ) 373 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_write : %d",store_queue_ptr_write); 374 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_read : %d",store_queue_ptr_read ); 375 // log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_empty : %d",store_queue_empty ); 376 log_printf(TRACE,Load_store_unit,FUNCTION," * reg_STORE_QUEUE_PTR_READ : %d",reg_STORE_QUEUE_PTR_READ); 377 378 if ((store_queue_ptr_write == store_queue_ptr_read) or 379 (store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ)) 380 // if (store_queue_empty) 371 381 { 372 log_printf(TRACE,Load_store_unit,FUNCTION," * index_store == reg_STORE_QUEUE_PTR_READ");382 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_write == store_queue_ptr_read"); 373 383 end_check = true; 374 384 change_state = true; … … 376 386 else 377 387 { 378 log_printf(TRACE,Load_store_unit,FUNCTION," * index_store != reg_STORE_QUEUE_PTR_READ");379 380 index_store = (index_store-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming381 382 log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store);388 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_write != store_queue_ptr_read"); 389 390 store_queue_ptr_write = (store_queue_ptr_write-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming 391 392 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_write : %d",store_queue_ptr_write); 383 393 384 394 // switch on store_queue state 385 switch (_store_queue[ index_store]._state)395 switch (_store_queue[store_queue_ptr_write]._state) 386 396 { 387 397 case STORE_QUEUE_VALID_NO_SPECULATIVE : … … 397 407 // Test thread id 398 408 if (_param->_have_port_context_id) 399 test_thread_id &= (_load_queue[index_load ]._context_id == _store_queue[index_store]._context_id);409 test_thread_id &= (_load_queue[index_load_queue]._context_id == _store_queue[store_queue_ptr_write]._context_id); 400 410 if (_param->_have_port_front_end_id) 401 test_thread_id &= (_load_queue[index_load ]._front_end_id == _store_queue[index_store]._front_end_id);411 test_thread_id &= (_load_queue[index_load_queue]._front_end_id == _store_queue[store_queue_ptr_write]._front_end_id); 402 412 if (_param->_have_port_ooo_engine_id) 403 test_thread_id &= (_load_queue[index_load ]._ooo_engine_id == _store_queue[index_store]._ooo_engine_id);413 test_thread_id &= (_load_queue[index_load_queue]._ooo_engine_id == _store_queue[store_queue_ptr_write]._ooo_engine_id); 404 414 405 415 if (test_thread_id) … … 408 418 409 419 log_printf(TRACE,Load_store_unit,FUNCTION," * load and store is the same thread."); 410 Tdcache_address_t load_addr = _load_queue [index_load ]._address;411 Tdcache_address_t store_addr = _store_queue[ index_store]._address;420 Tdcache_address_t load_addr = _load_queue [index_load_queue ]._address; 421 Tdcache_address_t store_addr = _store_queue[store_queue_ptr_write]._address; 412 422 413 423 log_printf(TRACE,Load_store_unit,FUNCTION," * load_addr : %.8x.",load_addr ); … … 435 445 bool is_big_endian = true; 436 446 437 Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ;438 Tgeneral_data_t store_data = _store_queue[ index_store]._wdata ;439 Tdcache_address_t check_hit_byte = _load_queue [index_load ]._check_hit_byte;440 Tcontrol_t check_hit = _load_queue [index_load ]._check_hit;441 uint32_t load_size_access = memory_size(_load_queue [index_load ]._operation)>>3;442 uint32_t store_size_access = memory_size(_store_queue[ index_store]._operation)>>3;447 Tgeneral_data_t load_data = _load_queue [index_load_queue ]._rdata ; 448 Tgeneral_data_t store_data = _store_queue[store_queue_ptr_write]._wdata ; 449 Tdcache_address_t check_hit_byte = _load_queue [index_load_queue ]._check_hit_byte; 450 Tcontrol_t check_hit = _load_queue [index_load_queue ]._check_hit; 451 uint32_t load_size_access = memory_size(_load_queue [index_load_queue ]._operation)>>3; 452 uint32_t store_size_access = memory_size(_store_queue[store_queue_ptr_write]._operation)>>3; 443 453 444 454 log_printf(TRACE,Load_store_unit,FUNCTION," * is_big_endian : %d",is_big_endian); … … 464 474 } 465 475 466 uint32_t store_nb_byte = (1<<memory_access(_store_queue[ index_store]._operation));476 uint32_t store_nb_byte = (1<<memory_access(_store_queue[store_queue_ptr_write]._operation)); 467 477 468 478 // Take interval to the store … … 473 483 log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_max : %d",store_num_byte_max); 474 484 475 // uint32_t load_nb_byte = (1<<memory_access(_load_queue[index_load ]._operation));485 // uint32_t load_nb_byte = (1<<memory_access(_load_queue[index_load_queue]._operation)); 476 486 477 487 // uint32_t load_num_byte_min = (load_addr & _param->_mask_address_lsb); … … 517 527 518 528 // // store duplicate = all store access can be see as full size_data store 519 // // uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load ]._operation));529 // // uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load_queue ]._operation)); 520 530 521 531 // // int32_t diff = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1)); … … 597 607 } 598 608 599 _load_queue[index_load ]._rdata = load_data;600 _load_queue[index_load ]._check_hit_byte = check_hit_byte;601 _load_queue[index_load ]._check_hit = check_hit;609 _load_queue[index_load_queue]._rdata = load_data; 610 _load_queue[index_load_queue]._check_hit_byte = check_hit_byte; 611 _load_queue[index_load_queue]._check_hit = check_hit; 602 612 603 613 log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (after) : 0x%.8x",load_data); … … 609 619 log_printf(TRACE,Load_store_unit,FUNCTION," * mask_check_hit_byte: %x",_param->_mask_check_hit_byte); 610 620 // The check is finish if all bit is set 611 end_check = (_load_queue[index_load ]._check_hit_byte == _param->_mask_check_hit_byte);621 end_check = (_load_queue[index_load_queue]._check_hit_byte == _param->_mask_check_hit_byte); 612 622 613 623 } … … 629 639 { 630 640 log_printf(TRACE,Load_store_unit,FUNCTION," * next"); 631 log_printf(TRACE,Load_store_unit,FUNCTION," * new store_queue_ptr_write : %d", index_store);641 log_printf(TRACE,Load_store_unit,FUNCTION," * new store_queue_ptr_write : %d",store_queue_ptr_write); 632 642 633 643 log_printf(TRACE,Load_store_unit,FUNCTION," * update reg_STORE_QUEUE_NB_CHECK"); 634 644 #ifdef DEBUG 635 if (reg_STORE_QUEUE_NB_CHECK [ index_store] == 0)645 if (reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] == 0) 636 646 throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n")); 637 647 #endif 638 reg_STORE_QUEUE_NB_CHECK [index_store] --; 639 640 // if (_load_queue[index_load]._store_queue_ptr_write == 0) 641 // _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1; 648 649 reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write] --; 650 651 log_printf(TRACE,Load_store_unit,FUNCTION," * reg_STORE_QUEUE_NB_CHECK 1 [%d] <- %d", store_queue_ptr_write,reg_STORE_QUEUE_NB_CHECK [store_queue_ptr_write]); 652 653 if ((store_queue_ptr_write == store_queue_ptr_read) or 654 (store_queue_ptr_write == reg_STORE_QUEUE_PTR_READ)) 655 { 656 // store_queue_empty = true; 657 end_check = true; 658 change_state = true; 659 } 660 661 // if (_load_queue[index_load_queue]._store_queue_ptr_write == 0) 662 // _load_queue[index_load_queue]._store_queue_ptr_write = _param->_size_store_queue-1; 642 663 // else 643 // _load_queue[index_load]._store_queue_ptr_write --; 644 _load_queue[index_load]._store_queue_ptr_write = index_store; // because the index store have be decrease 645 646 // FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "reg_STORE_QUEUE_PTR_READ" 647 if (index_store == reg_STORE_QUEUE_PTR_READ) 648 { 649 end_check = true; 650 change_state = true; 651 } 664 // _load_queue[index_load_queue]._store_queue_ptr_write --; 665 _load_queue[index_load_queue]._store_queue_ptr_write = store_queue_ptr_write; // because the index store have be decrease 666 _load_queue[index_load_queue]._store_queue_empty = store_queue_empty; // because the index store have be decrease 667 668 // FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "store_queue_ptr_read" 652 669 } 653 670 … … 657 674 log_printf(TRACE,Load_store_unit,FUNCTION," * end_check : %d",end_check); 658 675 659 log_printf(TRACE,Load_store_unit,FUNCTION," * state old : %s",toString(_load_queue[index_load ]._state).c_str());660 661 switch (_load_queue[index_load ]._state)676 log_printf(TRACE,Load_store_unit,FUNCTION," * state old : %s",toString(_load_queue[index_load_queue]._state).c_str()); 677 678 switch (_load_queue[index_load_queue]._state) 662 679 { 663 680 case LOAD_QUEUE_WAIT_CHECK : 664 681 { 665 682 if (end_check) 666 _load_queue[index_load ]._state = LOAD_QUEUE_WAIT ;683 _load_queue[index_load_queue]._state = LOAD_QUEUE_WAIT ; 667 684 break; 668 685 } … … 670 687 { 671 688 if (end_check) 672 _load_queue[index_load ]._state = LOAD_QUEUE_COMMIT;689 _load_queue[index_load_queue]._state = LOAD_QUEUE_COMMIT; 673 690 else 674 _load_queue[index_load ]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end691 _load_queue[index_load_queue]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end 675 692 break; 676 693 } … … 678 695 { 679 696 if (end_check) 680 _load_queue[index_load ]._state = LOAD_QUEUE_COMMIT;697 _load_queue[index_load_queue]._state = LOAD_QUEUE_COMMIT; 681 698 682 699 // check find a bypass. A speculative load have been committed : report a speculation miss. 683 if ((_load_queue[index_load ]._check_hit != 0) and684 (_load_queue[index_load ]._write_rd == 0) // is commit700 if ((_load_queue[index_load_queue]._check_hit != 0) and 701 (_load_queue[index_load_queue]._write_rd == 0) // is commit 685 702 ) 686 703 { 687 _load_queue[index_load ]._exception = EXCEPTION_MEMORY_MISS_SPECULATION;688 _load_queue[index_load ]._write_rd = 1; // write the good result704 _load_queue[index_load_queue]._exception = EXCEPTION_MEMORY_MISS_SPECULATION; 705 _load_queue[index_load_queue]._write_rd = 1; // write the good result 689 706 690 707 #ifdef STATISTICS … … 698 715 default : break; 699 716 } 700 log_printf(TRACE,Load_store_unit,FUNCTION," * state new : %s",toString(_load_queue[index_load]._state).c_str()); 701 log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",_load_queue[index_load]._exception); 702 703 if (end_check) 717 log_printf(TRACE,Load_store_unit,FUNCTION," * state new : %s",toString(_load_queue[index_load_queue]._state).c_str()); 718 log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",_load_queue[index_load_queue]._exception); 719 720 if (end_check// and not store_queue_empty 721 ) 704 722 { 705 723 log_printf(TRACE,Load_store_unit,FUNCTION," * end check, decrease all nb_check"); 706 724 707 uint32_t i= index_store;708 while (i!= reg_STORE_QUEUE_PTR_READ)725 uint32_t i=store_queue_ptr_write; 726 while (i!=store_queue_ptr_read) 709 727 { 710 728 i=((i==0)?_param->_size_store_queue:i)-1; … … 714 732 throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n")); 715 733 #endif 716 734 717 735 reg_STORE_QUEUE_NB_CHECK [i] --; 736 737 log_printf(TRACE,Load_store_unit,FUNCTION," * reg_STORE_QUEUE_NB_CHECK 2 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]); 738 718 739 //i=(i+1)%_param->_size_store_queue; 719 740 } 741 742 _load_queue[index_load_queue]._store_queue_empty = true; // end of check 720 743 } 721 744 } … … 856 879 _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 857 880 _store_queue [index]._address = address; 881 _store_queue [index]._send_commit = false; 858 882 859 883 // reordering data … … 895 919 _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 896 920 _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 921 _speculative_access_queue [index]._store_queue_ptr_read = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_READ [internal_MEMORY_IN_PORT]); 922 _speculative_access_queue [index]._store_queue_empty = PORT_READ(in_MEMORY_IN_STORE_QUEUE_EMPTY [internal_MEMORY_IN_PORT]); 897 923 _speculative_access_queue [index]._address = address; 898 924 // NOTE : is operation is a load, then they are a result and must write in the register file … … 954 980 bool have_exception = (exception != EXCEPTION_MEMORY_NONE); 955 981 bool need_check= false; 982 Tlsq_ptr_t store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write; 983 Tlsq_ptr_t store_queue_ptr_read = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_read ; 984 Tcontrol_t store_queue_empty = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_empty ; 956 985 957 986 if (have_exception) … … 962 991 { 963 992 // load and synchronisation 964 if (must_check(operation) )993 if (must_check(operation) and not store_queue_empty) 965 994 { 966 995 // load 967 996 need_check = true; 997 968 998 _load_queue [ptr_write]._state = LOAD_QUEUE_WAIT_CHECK; 969 999 } … … 984 1014 Tdcache_address_t address_lsb = (address & _param->_mask_address_lsb); 985 1015 Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte; 986 Tlsq_ptr_t store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;987 1016 988 1017 log_printf(TRACE,Load_store_unit,FUNCTION," * address : 0x%.8x", address); … … 998 1027 _load_queue [ptr_write]._operation = operation; 999 1028 _load_queue [ptr_write]._store_queue_ptr_write = store_queue_ptr_write; 1029 _load_queue [ptr_write]._store_queue_ptr_read = store_queue_ptr_read ; 1030 _load_queue [ptr_write]._store_queue_empty = store_queue_empty ; 1000 1031 _load_queue [ptr_write]._address = address; 1001 1032 _load_queue [ptr_write]._check_hit_byte = check_hit_byte; … … 1023 1054 1024 1055 // Only load need check 1025 if (need_check) 1056 if (need_check// and not store_queue_empty 1057 ) 1026 1058 // if (is_operation_memory_load(_load_queue [ptr_write]._operation)) 1027 1059 { 1028 1060 log_printf(TRACE,Load_store_unit,FUNCTION," * update nb_check"); 1029 1061 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_write : %d",store_queue_ptr_write); 1062 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_read : %d",store_queue_ptr_read ); 1063 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_empty : %d",store_queue_empty ); 1030 1064 log_printf(TRACE,Load_store_unit,FUNCTION," * reg_STORE_QUEUE_PTR_READ : %d",reg_STORE_QUEUE_PTR_READ); 1031 1065 1032 1066 uint32_t i=store_queue_ptr_write; 1033 while (i!= reg_STORE_QUEUE_PTR_READ)1067 while (i!=store_queue_ptr_read) 1034 1068 { 1035 1069 i=((i==0)?_param->_size_store_queue:i)-1; … … 1038 1072 1039 1073 reg_STORE_QUEUE_NB_CHECK [i] ++; 1074 1075 log_printf(TRACE,Load_store_unit,FUNCTION," * reg_STORE_QUEUE_NB_CHECK 3 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]); 1040 1076 } 1041 1077 } … … 1097 1133 1098 1134 1099 uint32_t i=_load_queue[packet_id]._store_queue_ptr_write; 1100 while (i!=reg_STORE_QUEUE_PTR_READ) 1101 { 1102 i=((i==0)?_param->_size_store_queue:i)-1; 1103 1135 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_write : %d", _load_queue[packet_id]._store_queue_ptr_write); 1136 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_read : %d", _load_queue[packet_id]._store_queue_ptr_read ); 1137 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_empty : %d", _load_queue[packet_id]._store_queue_empty ); 1138 1139 if (not _load_queue[packet_id]._store_queue_empty) 1140 { 1141 uint32_t i=_load_queue[packet_id]._store_queue_ptr_write; 1142 1143 while (i!=_load_queue[packet_id]._store_queue_ptr_read) 1144 { 1145 i=((i==0)?_param->_size_store_queue:i)-1; 1146 1104 1147 #ifdef DEBUG 1105 1106 1148 if (reg_STORE_QUEUE_NB_CHECK [i] == 0) 1149 throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n")); 1107 1150 #endif 1108 1109 reg_STORE_QUEUE_NB_CHECK [i] --; 1110 //i=(i+1)%_param->_size_store_queue; 1111 } 1151 1152 reg_STORE_QUEUE_NB_CHECK [i] --; 1153 1154 log_printf(TRACE,Load_store_unit,FUNCTION," * reg_STORE_QUEUE_NB_CHECK 4 [%d] <- %d", i,reg_STORE_QUEUE_NB_CHECK [i]); 1155 1156 //i=(i+1)%_param->_size_store_queue; 1157 } 1158 _load_queue[packet_id]._store_queue_empty = true; // end of check 1159 1160 } 1112 1161 } 1113 1162 else … … 1150 1199 uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; 1151 1200 1152 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d , %.2d %s",1201 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d %.1d, %.2d %s", 1153 1202 j, 1154 1203 _store_queue[j]._context_id , … … 1163 1212 //_store_queue[j]._num_reg_rd , 1164 1213 _store_queue[j]._exception , 1214 _store_queue[j]._send_commit , 1165 1215 reg_STORE_QUEUE_NB_CHECK [j] , 1166 1216 toString(_store_queue[j]._state).c_str()); … … 1174 1224 uint32_t j = (*_speculative_access_queue_control)[i]; 1175 1225 1176 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d , %.8x, %.1d %.4d, %.2d, %s",1226 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d %.4d %.1d, %.8x, %.1d %.4d, %.2d, %s", 1177 1227 j, 1178 1228 _speculative_access_queue[j]._context_id , … … 1183 1233 _speculative_access_queue[j]._load_queue_ptr_write, 1184 1234 _speculative_access_queue[j]._store_queue_ptr_write, 1235 _speculative_access_queue[j]._store_queue_ptr_read , 1236 _speculative_access_queue[j]._store_queue_empty , 1185 1237 _speculative_access_queue[j]._address , 1186 1238 _speculative_access_queue[j]._write_rd , … … 1198 1250 uint32_t j = i; 1199 1251 1200 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d , %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s",1252 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d %.1d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s", 1201 1253 j, 1202 1254 _load_queue[j]._context_id , … … 1206 1258 _load_queue[j]._operation , 1207 1259 _load_queue[j]._store_queue_ptr_write, 1260 _load_queue[j]._store_queue_ptr_read , 1261 _load_queue[j]._store_queue_empty , 1208 1262 _load_queue[j]._address , 1209 1263 _load_queue[j]._check_hit_byte ,
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