Changeset 123 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
- Timestamp:
- Jun 8, 2009, 10:43:30 PM (15 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r122 r123 53 53 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; 54 54 // reg_EVENT_FLUSH [i][j] = false; 55 55 // reg_EVENT_STOP [i][j] = false; 56 56 reg_EVENT_LAST [i][j] = false; 57 58 reg_EVENT_NEXT_STOP [i][j] = false; 57 59 58 60 // reg_PC_PREVIOUS [i][j] = (0x100-4)>>2; … … 86 88 // * and decod_queue is empty 87 89 // * and have an event or have a futur event 88 if (not reg_EVENT_CAN_RESTART [i][j] and89 (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and90 (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT)))91 reg_EVENT_CAN_RESTART [i][j] = true;90 // if (not reg_EVENT_CAN_RESTART [i][j] and 91 // (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and 92 // (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT))) 93 // reg_EVENT_CAN_RESTART [i][j] = true; 92 94 93 95 // Test event state … … 100 102 { 101 103 // A minor optimisation : test if wait_decod is previously empty. 102 if (not reg_EVENT_CAN_RESTART [i][j])103 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD;104 else104 // if (not reg_EVENT_CAN_RESTART [i][j]) 105 // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD; 106 // else 105 107 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; 106 108 } … … 108 110 break; 109 111 } 110 case COMMIT_EVENT_STATE_WAIT_DECOD :111 {112 // Wait flush of decod_queue.113 // Test if can restart now114 if (reg_EVENT_CAN_RESTART [i][j])115 {116 //reg_EVENT_FLUSH [i][j] = false;117 118 // A minor optimisation : test if the last element is already retire119 if (not reg_EVENT_LAST [i][j])120 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END;121 else122 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END;123 }124 break;125 }112 // case COMMIT_EVENT_STATE_WAIT_DECOD : 113 // { 114 // // Wait flush of decod_queue. 115 // // Test if can restart now 116 // if (reg_EVENT_CAN_RESTART [i][j]) 117 // { 118 // //reg_EVENT_FLUSH [i][j] = false; 119 120 // // A minor optimisation : test if the last element is already retire 121 // if (not reg_EVENT_LAST [i][j]) 122 // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; 123 // else 124 // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END; 125 // } 126 // break; 127 // } 126 128 case COMMIT_EVENT_STATE_WAIT_END : 127 129 { … … 138 140 139 141 // flush of re order buffer is finish 140 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT;141 142 reg_EVENT_LAST [i][j] = false; 143 144 if (not reg_EVENT_NEXT_STOP [i][j]) 145 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; 146 else 147 { 148 reg_EVENT_NEXT_STOP [i][j] = false; 149 reg_EVENT_PACKET [i][j] = reg_EVENT_NEXT_PACKET [i][j]; 150 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT; 151 // reg_EVENT_STOP [i][j] = true; 152 reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; 153 reg_EVENT_LAST_NUM_PTR [i][j] = reg_NUM_PTR_TAIL; 154 } 155 142 156 break; 143 157 } 144 158 //case COMMIT_EVENT_STATE_NO_EVENT : 159 //case COMMIT_EVENT_STATE_NOT_YET_EVENT : 145 160 default : break; 146 161 } … … 296 311 // * or present_event 297 312 // * and not can_restart (previous empty decod queue), because between the event_stop (branch_complete) and the state event (miss in head), many cycle is occured. 298 bool flush = ((// present event 299 ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or 300 (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or 301 // futur event 302 reg_EVENT_STOP [front_end_id][context_id]) 303 // can't restart 304 and not reg_EVENT_CAN_RESTART[front_end_id][context_id] 305 ); 306 307 if (flush) 308 { 309 // A new invalid instruction is push in rob -> new last instruction 310 reg_EVENT_LAST [front_end_id][context_id] = false; 311 reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank; 312 reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = ptr; 313 } 313 // bool flush = ((// present event 314 // ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or 315 // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) 316 // ) or 317 // futur event 318 // reg_EVENT_STOP [front_end_id][context_id]) 319 // // can't restart 320 // and not reg_EVENT_CAN_RESTART[front_end_id][context_id] 321 // ); 322 323 // if (flush) 324 // { 325 // // A new invalid instruction is push in rob -> new last instruction 326 // reg_EVENT_LAST [front_end_id][context_id] = false; 327 // reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank; 328 // reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = ptr; 329 // } 314 330 315 331 // Update pointer … … 359 375 // find the good entry !!! 360 376 entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; 377 378 log_printf(TRACE,Commit_unit,FUNCTION," * ptr : %d",entry->ptr); 361 379 362 380 //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); … … 480 498 481 499 // Commit an instruction ... 482 // Test if have an event (miss_speculation or exception) and not manage a previous event 483 // if yes, this instruction would modify state machine. Also stop Re Order Buffer 484 485 // bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id]; 486 bool flush = ((reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_EVENT) or 487 (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or 488 (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_WAIT_END)); 489 490 if ((have_exception or have_miss_speculation) and (not flush)) 500 // Test if have an event (miss_speculation or exception) 501 502 if (have_exception or have_miss_speculation) 491 503 { 504 // Two case : 505 // if no previous manage event -> generate an event 506 // if previous manage event -> next generate an event 507 508 // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; 509 bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or 510 // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or 511 (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END) or 512 (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_END) 513 ); 514 492 515 uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | i); 493 494 // test have a previous event detected (event_stop = 1) 495 // if yes, test if the actual event if "before (in order)" that the previous event 496 if (reg_EVENT_STOP [entry->front_end_id][entry->context_id]) 516 uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); 517 518 if (not flush) 497 519 { 498 // Compare packet_id (by construction instruction is insert in order by increase packet_id) 499 500 uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); 501 uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id]; 502 uint32_t _new = packet; 503 if (_old < _top) _old = _old+_param->_size_queue; 504 if (_new < _top) _new = _new+_param->_size_queue; 505 if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; 520 bool can = true; 521 // test have a previous event detected (event_stop = 1) 522 // if yes, test if the actual event if "before (in order)" that the previous event 523 if (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) 524 { 525 // Compare packet_id (by construction instruction is insert in order by increase packet_id) 526 527 uint32_t _old = reg_EVENT_PACKET [front_end_id][context_id]; 528 uint32_t _new = packet; 529 if (_old < _top) _old = _old+_param->_size_queue; 530 if (_new < _top) _new = _new+_param->_size_queue; 531 if (_new < _old) reg_EVENT_PACKET [front_end_id][context_id] = packet; 532 else can = false; 533 } 534 else 535 reg_EVENT_PACKET [front_end_id][context_id] = packet; 536 537 if (can) 538 { 539 // have an error, stop issue instruction 540 reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT; 541 // reg_EVENT_STOP [front_end_id][context_id] = true; 542 543 reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; 544 reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL; 545 } 506 546 } 507 547 else 508 reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; 509 510 // have an error, stop issue instruction 511 reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; 512 // reg_EVENT_NUM_BANK [entry->front_end_id][entry->context_id] = i; 513 // reg_EVENT_NUM_PTR [entry->front_end_id][entry->context_id] = entry->ptr; 514 515 // reg_EVENT_CAN_RESTART [entry->front_end_id][entry->context_id] = false; 516 reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; 517 reg_EVENT_LAST_NUM_PTR [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL; 548 { 549 bool find = true; 550 551 // already manage an event. 552 if (reg_EVENT_NEXT_STOP [front_end_id][context_id]) 553 { 554 // after last ? 555 uint32_t _old = reg_EVENT_NEXT_PACKET [front_end_id][context_id]; 556 uint32_t _new = packet; 557 if (_old < _top) _old = _old+_param->_size_queue; 558 if (_new < _top) _new = _new+_param->_size_queue; 559 if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet; 560 find = false; 561 } 562 else 563 { 564 // after last ? 565 uint32_t _old = ((reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [front_end_id][context_id]); 566 uint32_t _new = packet; 567 if (_old < _top) _old = _old+_param->_size_queue; 568 if (_new < _top) _new = _new+_param->_size_queue; 569 if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet; 570 find = false; 571 } 572 573 if (find) 574 reg_EVENT_NEXT_STOP [front_end_id][context_id] = true; // in all case : need stop 575 } 518 576 } 519 577 520 578 // Update Re Order Buffer 521 579 entry->state = state; … … 633 691 { 634 692 reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_EVENT; 635 // reg_EVENT_FLUSH [front_end_id][context_id] = true; 636 reg_EVENT_STOP [front_end_id][context_id] = false; // instruction flow can continue 637 // reg_EVENT_CAN_RESTART [front_end_id][context_id] = false; 693 // reg_EVENT_STOP [front_end_id][context_id] = false; // instruction flow can continue 638 694 reg_EVENT_LAST [front_end_id][context_id] = false; 639 695 // it the head ! 640 696 reg_EVENT_PACKET [front_end_id][context_id] = packet_id; 641 697 642 // If event is an load_miss, many instruction can be inserted.643 // -> new last instruction644 if (state == ROB_END_LOAD_MISS)645 {646 reg_EVENT_CAN_RESTART [front_end_id][context_id] = false;698 // // If event is an load_miss, many instruction can be inserted. 699 // // -> new last instruction 700 // if (state == ROB_END_LOAD_MISS) 701 // { 702 // // reg_EVENT_CAN_RESTART [front_end_id][context_id] = false; 647 703 648 reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;649 reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL;650 }704 // reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; 705 // reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL; 706 // } 651 707 } 652 708 … … 654 710 // * need event 655 711 // * packet id = last packet id 656 if ((reg_EVENT_STATE [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and 712 if (((reg_EVENT_STATE [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT ) and 713 (reg_EVENT_STATE [front_end_id][context_id] != COMMIT_EVENT_STATE_NOT_YET_EVENT)) and 657 714 (reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] == num_bank ) and 658 715 (reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] == entry->ptr )) … … 666 723 // Update pointer 667 724 reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank; 668 669 // Remove entry670 delete entry;671 _rob [num_bank].pop_front();672 725 673 726 // Reset watch dog timer because have transaction on retire interface … … 708 761 } 709 762 #endif 763 764 // Remove entry 765 delete entry; 766 _rob [num_bank].pop_front(); 710 767 } 711 768 } … … 775 832 if (miss) 776 833 { 834 bool can = true; 777 835 uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); 778 836 779 837 // test if this packet is before previous event 780 if (reg_EVENT_ST OP [entry->front_end_id][entry->context_id])838 if (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) 781 839 { 782 840 uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); … … 786 844 if (_new < _top) _new = _new+_param->_size_queue; 787 845 if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; 846 else can = false; 788 847 } 789 848 else 790 849 reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; 791 850 792 // In all case, stop instruction flow 793 reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; 794 // reg_EVENT_NUM_BANK [entry->front_end_id][entry->context_id] = num_bank; 795 // reg_EVENT_NUM_PTR [entry->front_end_id][entry->context_id] = entry->ptr; 796 797 reg_EVENT_CAN_RESTART [entry->front_end_id][entry->context_id] = false; 798 799 reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; 800 reg_EVENT_LAST_NUM_PTR [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL; 851 if (can) 852 { 853 // In all case, stop instruction flow 854 reg_EVENT_STATE [entry->front_end_id][entry->context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT; 855 // reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; 856 857 // reg_EVENT_CAN_RESTART [entry->front_end_id][entry->context_id] = false; 858 859 reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; 860 reg_EVENT_LAST_NUM_PTR [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL; 861 } 801 862 } 802 863 } … … 902 963 903 964 bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or 904 965 // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or 905 966 (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END)); 906 967 bool speculative = entry->speculative and not (depth == depth_min); … … 1005 1066 1006 1067 // Test if this instruction is the last of event 1007 if ((reg_EVENT_STATE [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and 1068 if (((reg_EVENT_STATE [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and 1069 (reg_EVENT_STATE [front_end_id][context_id] != COMMIT_EVENT_STATE_NOT_YET_EVENT)) and 1008 1070 (reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] == num_bank ) and 1009 1071 (reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] == entry->ptr )) … … 1044 1106 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s - %s",toString(reg_EVENT_STATE [i][j]).c_str(),toString(commit_event_state_to_event_state(reg_EVENT_STATE [i][j])).c_str()); 1045 1107 // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); 1046 1047 // 1048 1108 // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]); 1109 // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]); 1110 // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]); 1049 1111 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_PACKET : %d",reg_EVENT_PACKET[i][j]); 1050 1112 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d",reg_EVENT_LAST [i][j]); 1051 1113 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d (bank %d, ptr %d)",((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]); 1114 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NEXT_STOP : %d",reg_EVENT_NEXT_STOP [i][j]); 1115 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NEXT_PACKET : %d",reg_EVENT_NEXT_PACKET[i][j]); 1052 1116 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : %d",reg_NB_INST_COMMIT_ALL[i][j]); 1053 1117 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_MEM : %d",reg_NB_INST_COMMIT_MEM[i][j]); … … 1065 1129 } 1066 1130 1067 bool all_empty = false; 1131 bool all_empty = false; 1132 uint32_t nb_write_rd = 0; 1133 uint32_t nb_write_re = 0; 1134 1068 1135 while (not all_empty) 1069 1136 { … … 1078 1145 { 1079 1146 all_empty = false; 1147 1148 nb_write_rd += ((*it)->write_rd)?1:0; 1149 nb_write_re += ((*it)->write_re)?1:0; 1080 1150 1081 1151 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s", … … 1130 1200 } 1131 1201 } 1202 1203 log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_rd : %d",nb_write_rd); 1204 log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_re : %d",nb_write_re); 1132 1205 } 1133 1206 #endif
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