Changeset 135 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit
- Timestamp:
- Jul 17, 2009, 10:59:05 AM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp
r112 r135 70 70 { 71 71 ALLOC1_INTERFACE_BEGIN("address", OUT, SOUTH, _("Access at request icache."),_param->_nb_instruction); 72 INTERFACE1_TEST(false,_param->_nb_instruction); 72 73 73 74 ALLOC1_SIGNAL_OUT(out_ADDRESS_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); … … 96 97 { 97 98 ALLOC1_INTERFACE_BEGIN("predict", IN, NORTH, _("Request the prediction unit."),_param->_nb_instruction); 99 INTERFACE1_TEST(false,_param->_nb_instruction); 98 100 99 101 ALLOC1_SIGNAL_IN (in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_vhdl_body.cpp
r81 r135 23 23 { 24 24 log_printf(FUNC,Address_management,FUNCTION,"Begin"); 25 vhdl->set_body (""); 25 26 vhdl->set_body (0,""); 27 vhdl->set_comment(0,"========================================="); 28 vhdl->set_comment(0,"===== CONSTANT =========================="); 29 vhdl->set_comment(0,"========================================="); 30 vhdl->set_body (0,""); 31 vhdl->set_body (0,"internal_EVENT_ACK <= '1';"); 32 vhdl->set_body (0," out_EVENT_ACK <= internal_EVENT_ACK;"); 33 34 vhdl->set_body (0,""); 35 vhdl->set_comment(0,"========================================="); 36 vhdl->set_comment(0,"===== TRANSITION ========================"); 37 vhdl->set_comment(0,"========================================="); 38 vhdl->set_body (0,""); 39 40 vhdl->set_body (0,"TRANSITION : process (in_CLOCK)"); 41 42 vhdl->set_body (0,""); 43 vhdl->set_body (0,"variable var_PC_ACCESS_VAL : "+std_logic(1)+";"); 44 vhdl->set_body (0,"variable var_PC_ACCESS : "+std_logic(_param->_size_instruction_address)+";"); 45 vhdl->set_body (0,"variable var_PC_ACCESS_IS_DS_TAKE : "+std_logic(1)+";"); 46 vhdl->set_body (0,"variable var_PC_ACCESS_INSTRUCTION_ENABLE : Tinstruction_enable;"); 47 if (_param->_have_port_inst_ifetch_ptr) 48 vhdl->set_body (0,"variable var_PC_ACCESS_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); 49 vhdl->set_body (0,"variable var_PC_ACCESS_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); 50 if (_param->_have_port_depth) 51 vhdl->set_body (0,"variable var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); 52 vhdl->set_body (0,""); 53 vhdl->set_body (0,"variable var_PC_CURRENT_VAL : "+std_logic(1)+";"); 54 vhdl->set_body (0,"variable var_PC_CURRENT : "+std_logic(_param->_size_instruction_address)+";"); 55 vhdl->set_body (0,"variable var_PC_CURRENT_IS_DS_TAKE : "+std_logic(1)+";"); 56 vhdl->set_body (0,"variable var_PC_CURRENT_INSTRUCTION_ENABLE : Tinstruction_enable;"); 57 if (_param->_have_port_inst_ifetch_ptr) 58 vhdl->set_body (0,"variable var_PC_CURRENT_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); 59 vhdl->set_body (0,"variable var_PC_CURRENT_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); 60 if (_param->_have_port_depth) 61 vhdl->set_body (0,"variable var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); 62 vhdl->set_body (0,""); 63 vhdl->set_body (0,"variable var_PC_NEXT_VAL : "+std_logic(1)+";"); 64 vhdl->set_body (0,"variable var_PC_NEXT : "+std_logic(_param->_size_instruction_address)+";"); 65 vhdl->set_body (0,"variable var_PC_NEXT_IS_DS_TAKE : "+std_logic(1)+";"); 66 vhdl->set_body (0,"variable var_PC_NEXT_INSTRUCTION_ENABLE : Tinstruction_enable;"); 67 if (_param->_have_port_inst_ifetch_ptr) 68 vhdl->set_body (0,"variable var_PC_NEXT_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); 69 vhdl->set_body (0,"variable var_PC_NEXT_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); 70 if (_param->_have_port_depth) 71 vhdl->set_body (0,"variable var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); 72 vhdl->set_body (0,""); 73 vhdl->set_body (0,"variable var_PC_NEXT_NEXT_VAL : "+std_logic(1)+";"); 74 vhdl->set_body (0,"variable var_PC_NEXT_NEXT : "+std_logic(_param->_size_instruction_address)+";"); 75 vhdl->set_body (0,"variable var_PC_NEXT_NEXT_IS_DS_TAKE : "+std_logic(1)+";"); 76 // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_INSTRUCTION_ENABLE : Tinstruction_enable;"); 77 // if (_param->_have_port_inst_ifetch_ptr) 78 // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); 79 // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); 80 // if (_param->_have_port_depth) 81 // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); 82 vhdl->set_body (0,""); 83 vhdl->set_body (0,"begin -- TRANSITION"); 84 vhdl->set_body (1,"if (in_CLOCK'event and in_CLOCK = '1')then"); 85 vhdl->set_body (1,""); 86 vhdl->set_body (2,"if (in_NRESET = '0') then"); 87 vhdl->set_body (3,""); 88 89 { 90 vhdl->set_body (3,"reg_PC_ACCESS_VAL <= '0';"); 91 #ifdef SYSTEMC_VHDL_COMPATIBILITY 92 vhdl->set_body (3,"reg_PC_ACCESS <= "+std_logic_cst(_param->_size_instruction_address,0)+";"); 93 #endif 94 vhdl->set_body (3,"reg_PC_CURRENT_VAL <= '0';"); 95 #ifdef SYSTEMC_VHDL_COMPATIBILITY 96 vhdl->set_body (3,"reg_PC_CURRENT <= "+std_logic_cst(_param->_size_instruction_address,0)+";"); 97 #endif 98 vhdl->set_body (3,"reg_PC_NEXT_VAL <= '1';"); 99 vhdl->set_body (3,"reg_PC_NEXT <= "+std_logic_cst(_param->_size_instruction_address,0x100>>2)+";"); 100 vhdl->set_body (3,"reg_PC_NEXT_IS_DS_TAKE <= '0';"); 101 uint32_t index = reg_PC_NEXT % _param->_nb_instruction; 102 for (uint32_t i=0; i<_param->_nb_instruction; i++) 103 { 104 std::string value = (i != index)?"'0'":"'1'"; 105 vhdl->set_body (3,"reg_PC_NEXT_INSTRUCTION_ENABLE ("+toString(i)+") <= "+value+";"); 106 } 107 if (_param->_have_port_inst_ifetch_ptr) 108 vhdl->set_body (3,"reg_PC_NEXT_INST_IFETCH_PTR <= "+std_logic_cst(_param->_size_inst_ifetch_ptr,0)+";"); 109 vhdl->set_body (3,"reg_PC_NEXT_BRANCH_STATE <= "+std_logic_cst(_param->_size_branch_state ,0)+";"); 110 if (_param->_have_port_depth) 111 vhdl->set_body (3,"reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID <= "+std_logic_cst(_param->_size_depth ,0)+";"); 112 vhdl->set_body (3,"reg_PC_NEXT_NEXT_VAL <= '0';"); 113 #ifdef SYSTEMC_VHDL_COMPATIBILITY 114 vhdl->set_body (3,"reg_PC_NEXT_NEXT <= "+std_logic_cst(_param->_size_instruction_address,0)+";"); 115 #endif 116 } 117 vhdl->set_body (3,""); 118 vhdl->set_body (2,"else"); 119 120 vhdl->set_body (3,"var_PC_ACCESS_VAL := reg_PC_ACCESS_VAL ;"); 121 vhdl->set_body (3,"var_PC_ACCESS := reg_PC_ACCESS ;"); 122 vhdl->set_body (3,"var_PC_ACCESS_IS_DS_TAKE := reg_PC_ACCESS_IS_DS_TAKE ;"); 123 vhdl->set_body (3,"var_PC_ACCESS_INSTRUCTION_ENABLE := reg_PC_ACCESS_INSTRUCTION_ENABLE ;"); 124 if (_param->_have_port_inst_ifetch_ptr) 125 vhdl->set_body (3,"var_PC_ACCESS_INST_IFETCH_PTR := reg_PC_ACCESS_INST_IFETCH_PTR ;"); 126 vhdl->set_body (3,"var_PC_ACCESS_BRANCH_STATE := reg_PC_ACCESS_BRANCH_STATE ;"); 127 if (_param->_have_port_depth) 128 vhdl->set_body (3,"var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID := reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID ;"); 129 vhdl->set_body (3,""); 130 vhdl->set_body (3,"var_PC_CURRENT_VAL := reg_PC_CURRENT_VAL ;"); 131 vhdl->set_body (3,"var_PC_CURRENT := reg_PC_CURRENT ;"); 132 vhdl->set_body (3,"var_PC_CURRENT_IS_DS_TAKE := reg_PC_CURRENT_IS_DS_TAKE ;"); 133 vhdl->set_body (3,"var_PC_CURRENT_INSTRUCTION_ENABLE := reg_PC_CURRENT_INSTRUCTION_ENABLE ;"); 134 if (_param->_have_port_inst_ifetch_ptr) 135 vhdl->set_body (3,"var_PC_CURRENT_INST_IFETCH_PTR := reg_PC_CURRENT_INST_IFETCH_PTR ;"); 136 vhdl->set_body (3,"var_PC_CURRENT_BRANCH_STATE := reg_PC_CURRENT_BRANCH_STATE ;"); 137 if (_param->_have_port_depth) 138 vhdl->set_body (3,"var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID := reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID ;"); 139 vhdl->set_body (3,""); 140 vhdl->set_body (3,"var_PC_NEXT_VAL := reg_PC_NEXT_VAL ;"); 141 vhdl->set_body (3,"var_PC_NEXT := reg_PC_NEXT ;"); 142 vhdl->set_body (3,"var_PC_NEXT_IS_DS_TAKE := reg_PC_NEXT_IS_DS_TAKE ;"); 143 vhdl->set_body (3,"var_PC_NEXT_INSTRUCTION_ENABLE := reg_PC_NEXT_INSTRUCTION_ENABLE ;"); 144 if (_param->_have_port_inst_ifetch_ptr) 145 vhdl->set_body (3,"var_PC_NEXT_INST_IFETCH_PTR := reg_PC_NEXT_INST_IFETCH_PTR ;"); 146 vhdl->set_body (3,"var_PC_NEXT_BRANCH_STATE := reg_PC_NEXT_BRANCH_STATE ;"); 147 if (_param->_have_port_depth) 148 vhdl->set_body (3,"var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID := reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); 149 vhdl->set_body (3,""); 150 vhdl->set_body (3,"var_PC_NEXT_NEXT_VAL := reg_PC_NEXT_NEXT_VAL ;"); 151 vhdl->set_body (3,"var_PC_NEXT_NEXT := reg_PC_NEXT_NEXT ;"); 152 vhdl->set_body (3,"var_PC_NEXT_NEXT_IS_DS_TAKE := reg_PC_NEXT_NEXT_IS_DS_TAKE ;"); 153 // vhdl->set_body (3,"var_PC_NEXT_NEXT_INSTRUCTION_ENABLE := reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE ;"); 154 // if (_param->_have_port_inst_ifetch_ptr) 155 // vhdl->set_body (3,"var_PC_NEXT_NEXT_INST_IFETCH_PTR := reg_PC_NEXT_NEXT_INST_IFETCH_PTR ;"); 156 // vhdl->set_body (3,"var_PC_NEXT_NEXT_BRANCH_STATE := reg_PC_NEXT_NEXT_BRANCH_STATE ;"); 157 // if (_param->_have_port_depth) 158 // vhdl->set_body (3,"var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID := reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); 159 160 { 161 vhdl->set_comment(3,"========================================="); 162 vhdl->set_comment(3,"===== PREDICT ==========================="); 163 vhdl->set_comment(3,"========================================="); 164 165 vhdl->set_body (3,"if ((internal_PREDICT_VAL and in_PREDICT_ACK) = '1') then"); 166 vhdl->set_body (4,"if (var_PC_NEXT_IS_DS_TAKE = '1') then"); 167 if (_param->_have_port_inst_ifetch_ptr) 168 vhdl->set_body (5,"var_PC_CURRENT_INST_IFETCH_PTR := in_PREDICT_INST_IFETCH_PTR;"); 169 vhdl->set_body (5,"var_PC_CURRENT_BRANCH_STATE := in_PREDICT_BRANCH_STATE;"); 170 if (_param->_have_port_depth) 171 vhdl->set_body (5,"var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID := in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;"); 172 vhdl->set_body (5,"else"); 173 if (_param->_have_port_inst_ifetch_ptr) 174 vhdl->set_body (5,"var_PC_NEXT_INST_IFETCH_PTR := in_PREDICT_INST_IFETCH_PTR;"); 175 vhdl->set_body (5,"var_PC_NEXT_BRANCH_STATE := in_PREDICT_BRANCH_STATE;"); 176 if (_param->_have_port_depth) 177 vhdl->set_body (5,"var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID := in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;"); 178 vhdl->set_body (4,"end if;"); 179 180 vhdl->set_body (4,"var_PC_NEXT_NEXT_VAL := '1'; -- address is valid"); 181 vhdl->set_body (4,"var_PC_NEXT_NEXT := in_PREDICT_PC_NEXT;"); 182 vhdl->set_body (4,"var_PC_NEXT_NEXT_IS_DS_TAKE := in_PREDICT_PC_NEXT_IS_DS_TAKE;"); 183 for (uint32_t i=0; i<_param->_nb_instruction; i++) 184 vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE;"); 185 186 vhdl->set_body (3,"end if;"); 187 } 188 189 { 190 vhdl->set_comment(3,"========================================="); 191 vhdl->set_comment(3,"===== ADDRESS ==========================="); 192 vhdl->set_comment(3,"========================================="); 193 194 vhdl->set_body (3,"if ((internal_ADDRESS_VAL and in_ADDRESS_ACK) = '1') then"); 195 196 vhdl->set_body (4,"var_PC_ACCESS_VAL := '0'; -- transaction with icache"); 197 198 vhdl->set_body (3,"end if;"); 199 } 200 201 { 202 vhdl->set_comment(3,"========================================="); 203 vhdl->set_comment(3,"===== Shift Register ===================="); 204 vhdl->set_comment(3,"========================================="); 205 206 vhdl->set_body (3,"if ((var_PC_NEXT_NEXT_VAL and var_PC_NEXT_VAL and var_PC_CURRENT_VAL and not var_PC_ACCESS_VAL) = '1') then"); 207 vhdl->set_body (4,"var_PC_ACCESS_VAL := '1'; -- new request"); 208 vhdl->set_body (4,"var_PC_CURRENT_VAL := '0'; -- invalid current"); 209 vhdl->set_body (4,"var_PC_ACCESS := var_PC_CURRENT;"); 210 vhdl->set_body (4,"var_PC_ACCESS_IS_DS_TAKE := var_PC_CURRENT_IS_DS_TAKE;"); 211 if (_param->_have_port_inst_ifetch_ptr) 212 vhdl->set_body (4,"var_PC_ACCESS_INST_IFETCH_PTR := var_PC_CURRENT_INST_IFETCH_PTR;"); 213 vhdl->set_body (4,"var_PC_ACCESS_BRANCH_STATE := var_PC_CURRENT_BRANCH_STATE;"); 214 if (_param->_have_port_depth) 215 vhdl->set_body (4,"var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID := var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID;"); 216 // for (uint32_t i=0; i<_param->_nb_instruction; i++) 217 // vhdl->set_body (4,"var_PC_ACCESS_INSTRUCTION_ENABLE("+toString(i)+") := var_PC_CURRENT_INSTRUCTION_ENABLE("+toString(i)+");"); 218 vhdl->set_body (4,"var_PC_ACCESS_INSTRUCTION_ENABLE := var_PC_CURRENT_INSTRUCTION_ENABLE;"); 219 vhdl->set_body (3,"end if;"); 220 221 vhdl->set_body (3,"if ((var_PC_NEXT_NEXT_VAL and var_PC_NEXT_VAL and not var_PC_CURRENT_VAL) = '1') then"); 222 vhdl->set_body (4,"var_PC_CURRENT_VAL := '1'; -- new request"); 223 vhdl->set_body (4,"var_PC_NEXT_VAL := '0'; -- invalid next"); 224 vhdl->set_body (4,"var_PC_CURRENT := var_PC_NEXT;"); 225 vhdl->set_body (4,"var_PC_CURRENT_IS_DS_TAKE := var_PC_NEXT_IS_DS_TAKE;"); 226 if (_param->_have_port_inst_ifetch_ptr) 227 vhdl->set_body (4,"var_PC_CURRENT_INST_IFETCH_PTR := var_PC_NEXT_INST_IFETCH_PTR;"); 228 vhdl->set_body (4,"var_PC_CURRENT_BRANCH_STATE := var_PC_NEXT_BRANCH_STATE;"); 229 if (_param->_have_port_depth) 230 vhdl->set_body (4,"var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID := var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;"); 231 // for (uint32_t i=0; i<_param->_nb_instruction; i++) 232 // vhdl->set_body (4,"var_PC_CURRENT_INSTRUCTION_ENABLE("+toString(i)+") := var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+");"); 233 vhdl->set_body (4,"var_PC_CURRENT_INSTRUCTION_ENABLE := var_PC_NEXT_INSTRUCTION_ENABLE;"); 234 vhdl->set_body (3,"end if;"); 235 236 vhdl->set_body (3,"if ((var_PC_NEXT_NEXT_VAL and not var_PC_NEXT_VAL) = '1') then"); 237 vhdl->set_body (4,"var_PC_NEXT_VAL := '1'; -- new request"); 238 vhdl->set_body (4,"var_PC_NEXT_NEXT_VAL := '0'; -- invalid next_next"); 239 vhdl->set_body (4,"var_PC_NEXT := var_PC_NEXT_NEXT;"); 240 vhdl->set_body (4,"var_PC_NEXT_IS_DS_TAKE := var_PC_NEXT_NEXT_IS_DS_TAKE;"); 241 // if (_param->_have_port_inst_ifetch_ptr) 242 // vhdl->set_body (4,"var_PC_NEXT_INST_IFETCH_PTR := var_PC_NEXT_NEXT_INST_IFETCH_PTR;"); 243 // vhdl->set_body (4,"var_PC_NEXT_BRANCH_STATE := var_PC_NEXT_NEXT_BRANCH_STATE;"); 244 // if (_param->_have_port_depth) 245 // vhdl->set_body (4,"var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID := var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID;"); 246 // for (uint32_t i=0; i<_param->_nb_instruction; i++) 247 // vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := var_PC_NEXT_NEXT_INSTRUCTION_ENABLE("+toString(i)+");"); 248 // vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE := var_PC_NEXT_NEXT_INSTRUCTION_ENABLE;"); 249 vhdl->set_body (3,"end if;"); 250 } 251 252 { 253 vhdl->set_comment(3,"========================================="); 254 vhdl->set_comment(3,"===== EVENT ============================="); 255 vhdl->set_comment(3,"========================================="); 256 257 vhdl->set_body (3,"if ((in_EVENT_VAL and internal_EVENT_ACK) = '1') then"); 258 vhdl->set_body (4,"var_PC_ACCESS_VAL := '0';"); 259 vhdl->set_body (4,"var_PC_CURRENT_VAL := '0';"); 260 vhdl->set_body (4,"var_PC_NEXT_VAL := '1';"); 261 vhdl->set_body (4,"var_PC_NEXT := in_EVENT_ADDRESS;"); 262 vhdl->set_body (4,"var_PC_NEXT_IS_DS_TAKE := in_EVENT_IS_DS_TAKE;"); 263 264 if (is_power2(_param->_nb_instruction)) 265 { 266 uint32_t size = log2(_param->_nb_instruction); 267 268 if (size != 0) 269 { 270 std::string range = "var_PC_NEXT"+std_logic_range(size-1,0); 271 272 for (uint32_t i=0; i<_param->_nb_instruction; i++) 273 { 274 vhdl->set_body (4,"if ("+range+" = "+std_logic_cst(size,i)+") then"); 275 vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := '1';"); 276 vhdl->set_body (4,"else"); 277 vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := '0';"); 278 vhdl->set_body (4,"end if;"); 279 } 280 } 281 else 282 vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE(0) := '1';"); 283 } 284 else 285 { 286 throw ERRORMORPHEO(FUNCTION,_("Not Yet supported, Comming Soon.")); 287 } 288 289 vhdl->set_body (4,"var_PC_NEXT_NEXT_VAL := in_EVENT_ADDRESS_NEXT_VAL;"); 290 vhdl->set_body (4,"var_PC_NEXT_NEXT := in_EVENT_ADDRESS_NEXT;"); 291 vhdl->set_body (4,"var_PC_NEXT_NEXT_IS_DS_TAKE := '0';"); 292 293 vhdl->set_body (3,"end if;"); 294 } 295 296 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 297 vhdl->set_comment(3,"WRITE Register"); 298 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 299 300 vhdl->set_body (3,"reg_PC_ACCESS_VAL <= var_PC_ACCESS_VAL ;"); 301 vhdl->set_body (3,"reg_PC_ACCESS <= var_PC_ACCESS ;"); 302 vhdl->set_body (3,"reg_PC_ACCESS_IS_DS_TAKE <= var_PC_ACCESS_IS_DS_TAKE ;"); 303 vhdl->set_body (3,"reg_PC_ACCESS_INSTRUCTION_ENABLE <= var_PC_ACCESS_INSTRUCTION_ENABLE ;"); 304 if (_param->_have_port_inst_ifetch_ptr) 305 vhdl->set_body (3,"reg_PC_ACCESS_INST_IFETCH_PTR <= var_PC_ACCESS_INST_IFETCH_PTR ;"); 306 vhdl->set_body (3,"reg_PC_ACCESS_BRANCH_STATE <= var_PC_ACCESS_BRANCH_STATE ;"); 307 if (_param->_have_port_depth) 308 vhdl->set_body (3,"reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID <= var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID ;"); 309 vhdl->set_body (3,""); 310 vhdl->set_body (3,"reg_PC_CURRENT_VAL <= var_PC_CURRENT_VAL ;"); 311 vhdl->set_body (3,"reg_PC_CURRENT <= var_PC_CURRENT ;"); 312 vhdl->set_body (3,"reg_PC_CURRENT_IS_DS_TAKE <= var_PC_CURRENT_IS_DS_TAKE ;"); 313 vhdl->set_body (3,"reg_PC_CURRENT_INSTRUCTION_ENABLE <= var_PC_CURRENT_INSTRUCTION_ENABLE ;"); 314 if (_param->_have_port_inst_ifetch_ptr) 315 vhdl->set_body (3,"reg_PC_CURRENT_INST_IFETCH_PTR <= var_PC_CURRENT_INST_IFETCH_PTR ;"); 316 vhdl->set_body (3,"reg_PC_CURRENT_BRANCH_STATE <= var_PC_CURRENT_BRANCH_STATE ;"); 317 if (_param->_have_port_depth) 318 vhdl->set_body (3,"reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID <= var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID ;"); 319 vhdl->set_body (3,""); 320 vhdl->set_body (3,"reg_PC_NEXT_VAL <= var_PC_NEXT_VAL ;"); 321 vhdl->set_body (3,"reg_PC_NEXT <= var_PC_NEXT ;"); 322 vhdl->set_body (3,"reg_PC_NEXT_IS_DS_TAKE <= var_PC_NEXT_IS_DS_TAKE ;"); 323 vhdl->set_body (3,"reg_PC_NEXT_INSTRUCTION_ENABLE <= var_PC_NEXT_INSTRUCTION_ENABLE ;"); 324 if (_param->_have_port_inst_ifetch_ptr) 325 vhdl->set_body (3,"reg_PC_NEXT_INST_IFETCH_PTR <= var_PC_NEXT_INST_IFETCH_PTR ;"); 326 vhdl->set_body (3,"reg_PC_NEXT_BRANCH_STATE <= var_PC_NEXT_BRANCH_STATE ;"); 327 if (_param->_have_port_depth) 328 vhdl->set_body (3,"reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID <= var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); 329 vhdl->set_body (3,""); 330 vhdl->set_body (3,"reg_PC_NEXT_NEXT_VAL <= var_PC_NEXT_NEXT_VAL ;"); 331 vhdl->set_body (3,"reg_PC_NEXT_NEXT <= var_PC_NEXT_NEXT ;"); 332 vhdl->set_body (3,"reg_PC_NEXT_NEXT_IS_DS_TAKE <= var_PC_NEXT_NEXT_IS_DS_TAKE ;"); 333 // vhdl->set_body (3,"reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE <= var_PC_NEXT_NEXT_INSTRUCTION_ENABLE ;"); 334 // if (_param->_have_port_inst_ifetch_ptr) 335 // vhdl->set_body (3,"reg_PC_NEXT_NEXT_INST_IFETCH_PTR <= var_PC_NEXT_NEXT_INST_IFETCH_PTR ;"); 336 // vhdl->set_body (3,"reg_PC_NEXT_NEXT_BRANCH_STATE <= var_PC_NEXT_NEXT_BRANCH_STATE ;"); 337 // if (_param->_have_port_depth) 338 // vhdl->set_body (3,"reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID <= var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); 339 340 341 vhdl->set_body (2,"end if; -- reset"); 342 vhdl->set_body (1,"end if; -- clock"); 343 vhdl->set_body (0,"end process; -- TRANSITION"); 344 345 vhdl->set_comment(0,"========================================="); 346 vhdl->set_comment(0,"===== ADDRESS ==========================="); 347 vhdl->set_comment(0,"========================================="); 348 349 vhdl->set_body (0,"internal_ADDRESS_VAL <= reg_PC_ACCESS_VAL;"); 350 vhdl->set_body (0," out_ADDRESS_VAL <= internal_ADDRESS_VAL;"); 351 352 if (is_power2(_param->_nb_instruction)) 353 { 354 uint32_t size = log2(_param->_nb_instruction); 355 356 vhdl->set_body (0,"out_ADDRESS_INSTRUCTION_ADDRESS <= reg_PC_ACCESS and not "+std_logic_cst(_param->_size_instruction_address,(1<<size)-1)+";"); 357 } 358 else 359 { 360 throw ERRORMORPHEO(FUNCTION,_("Not Yet supported, Comming Soon.")); 361 } 362 363 364 if (_param->_have_port_inst_ifetch_ptr) 365 vhdl->set_body (0,"out_ADDRESS_INST_IFETCH_PTR <= reg_PC_ACCESS_INST_IFETCH_PTR;"); 366 vhdl->set_body (0,"out_ADDRESS_BRANCH_STATE <= reg_PC_ACCESS_BRANCH_STATE;"); 367 if (_param->_have_port_depth) 368 vhdl->set_body (0,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID<= reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID;"); 369 for (uint32_t i=0; i<_param->_nb_instruction; i++) 370 vhdl->set_body (0,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE <= reg_PC_ACCESS_INSTRUCTION_ENABLE ("+toString(i)+");"); 371 372 vhdl->set_comment(0,"========================================="); 373 vhdl->set_comment(0,"===== PREDICT ==========================="); 374 vhdl->set_comment(0,"========================================="); 375 376 vhdl->set_body (0,"internal_PREDICT_VAL <= not reg_PC_NEXT_NEXT_VAL;"); 377 vhdl->set_body (0," out_PREDICT_VAL <= internal_PREDICT_VAL; "); 378 vhdl->set_body (0,"out_PREDICT_PC_PREVIOUS <= reg_PC_CURRENT; "); 379 vhdl->set_body (0,"out_PREDICT_PC_CURRENT <= reg_PC_NEXT; "); 380 vhdl->set_body (0,"out_PREDICT_PC_CURRENT_IS_DS_TAKE <= reg_PC_NEXT_IS_DS_TAKE;"); 381 26 382 log_printf(FUNC,Address_management,FUNCTION,"End"); 27 383 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_vhdl_declaration.cpp
r81 r135 23 23 { 24 24 log_printf(FUNC,Address_management,FUNCTION,"Begin"); 25 26 vhdl->set_type ("Tinstruction_enable ","array "+_std_logic_range(_param->_nb_instruction)+" of std_logic"); 27 28 vhdl->set_signal ("reg_PC_ACCESS_VAL ", 1); 29 vhdl->set_signal ("reg_PC_ACCESS ", _param->_size_instruction_address); 30 vhdl->set_signal ("reg_PC_ACCESS_IS_DS_TAKE ", 1); 31 vhdl->set_signal ("reg_PC_ACCESS_INSTRUCTION_ENABLE ", "Tinstruction_enable"); 32 if (_param->_have_port_inst_ifetch_ptr) 33 vhdl->set_signal ("reg_PC_ACCESS_INST_IFETCH_PTR ", _param->_size_inst_ifetch_ptr); 34 vhdl->set_signal ("reg_PC_ACCESS_BRANCH_STATE ", _param->_size_branch_state); 35 if (_param->_have_port_depth) 36 vhdl->set_signal ("reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID ", _param->_size_depth); 37 38 39 vhdl->set_signal ("reg_PC_CURRENT_VAL ", 1); 40 vhdl->set_signal ("reg_PC_CURRENT ", _param->_size_instruction_address); 41 vhdl->set_signal ("reg_PC_CURRENT_IS_DS_TAKE ", 1); 42 vhdl->set_signal ("reg_PC_CURRENT_INSTRUCTION_ENABLE ", "Tinstruction_enable"); 43 if (_param->_have_port_inst_ifetch_ptr) 44 vhdl->set_signal ("reg_PC_CURRENT_INST_IFETCH_PTR ",_param->_size_inst_ifetch_ptr); 45 vhdl->set_signal ("reg_PC_CURRENT_BRANCH_STATE ", _param->_size_branch_state); 46 if (_param->_have_port_depth) 47 vhdl->set_signal ("reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID ", _param->_size_depth); 48 49 vhdl->set_signal ("reg_PC_NEXT_VAL ", 1); 50 vhdl->set_signal ("reg_PC_NEXT ", _param->_size_instruction_address); 51 vhdl->set_signal ("reg_PC_NEXT_IS_DS_TAKE ", 1); 52 vhdl->set_signal ("reg_PC_NEXT_INSTRUCTION_ENABLE ", "Tinstruction_enable"); 53 if (_param->_have_port_inst_ifetch_ptr) 54 vhdl->set_signal ("reg_PC_NEXT_INST_IFETCH_PTR ",_param->_size_inst_ifetch_ptr); 55 vhdl->set_signal ("reg_PC_NEXT_BRANCH_STATE ", _param->_size_branch_state); 56 if (_param->_have_port_depth) 57 vhdl->set_signal ("reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID ", _param->_size_depth); 58 59 vhdl->set_signal ("reg_PC_NEXT_NEXT_VAL ", 1); 60 vhdl->set_signal ("reg_PC_NEXT_NEXT ", _param->_size_instruction_address); 61 vhdl->set_signal ("reg_PC_NEXT_NEXT_IS_DS_TAKE ", 1); 62 // vhdl->set_signal ("reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE ", "Tinstruction_enable"); 63 // if (_param->_have_port_inst_ifetch_ptr) 64 // vhdl->set_signal ("reg_PC_NEXT_NEXT_INST_IFETCH_PTR ",_param->_size_inst_ifetch_ptr); 65 // vhdl->set_signal ("reg_PC_NEXT_NEXT_BRANCH_STATE ", _param->_size_branch_state); 66 // if (_param->_have_port_depth) 67 // vhdl->set_signal ("reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID", _param->_size_depth); 68 69 vhdl->set_signal ("internal_PREDICT_VAL ", 1); 70 vhdl->set_signal ("internal_ADDRESS_VAL ", 1); 71 vhdl->set_signal ("internal_EVENT_ACK ", 1); 72 25 73 log_printf(FUNC,Address_management,FUNCTION,"End"); 26 74 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h
r128 r135 27 27 IFETCH_QUEUE_STATE_ERROR_WAIT_RSP // A event occure -> flush the queue but, ack rsp 28 28 } ifetch_queue_state_t; 29 30 #define IFETCH_QUEUE_STATE_SIZE 2 29 31 30 32 class ifetch_queue_entry_t -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_vhdl_body.cpp
r81 r135 23 23 { 24 24 log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); 25 vhdl->set_body (""); 25 26 vhdl->set_comment(0,"========================================="); 27 vhdl->set_comment(0,"===== CONSTANT =========================="); 28 vhdl->set_comment(0,"========================================="); 29 vhdl->set_body (0,""); 30 vhdl->set_body (0,"internal_ICACHE_RSP_ACK <= '1';"); 31 vhdl->set_body (0,"internal_EVENT_RESET_ACK <= '1';"); 32 vhdl->set_body (0,"out_EVENT_RESET_ACK <= '1';"); 33 vhdl->set_body (0,"out_ICACHE_RSP_ACK <= '1';"); 34 vhdl->set_body (0,""); 35 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 36 vhdl->set_comment(0,"TRANSLATION "); 37 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 38 vhdl->set_body (0,"TRANSITION : process (in_CLOCK)"); 39 vhdl->set_body (0,"variable have_instruction_decod : std_logic;"); 40 vhdl->set_body (0,"variable have_instruction_enable : std_logic;"); 41 // vhdl->set_body (0,"variable reg_INSTRUCTION_ENABLE_VAR : std_logic;"); 42 if (_param->_size_queue>1) { 43 vhdl->set_body (0,"variable var_PTR_READ :"+ std_logic(log2(_param->_size_queue))+";"); 44 vhdl->set_body (0,"variable var_PTR_WRITE :"+ std_logic(log2(_param->_size_queue))+";"); 45 } 46 // vhdl->set_body (0,"variable var_EMPTY : std_logic;"); 47 vhdl->set_body (0,"variable var_STATE : Tstate;"); 48 vhdl->set_body (0,"variable var_INSTRUCTION_ENABLE : Tenable;"); 49 vhdl->set_body (0,"variable var_ADDRESS : Tadress;"); 50 if(_param->_have_port_inst_ifetch_ptr) 51 vhdl->set_body (0,"variable var_INST_IFETCH_PTR : Tinst_ptr;"); 52 vhdl->set_body (0,"variable var_BRANCH_STATE : Tbranch_state;"); 53 if(_param->_have_port_depth) 54 vhdl->set_body (0,"variable var_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); 55 // vhdl->set_body (0,"variable var_internal_ICACHE_RSP_ACK : std_logic;"); 56 if (_param->_have_port_ifetch_queue_ptr) 57 vhdl->set_body (0,"variable var_internal_ICACHE_RSP_PACKET_ID : "+std_logic(_param->_size_ifetch_queue_ptr)+";"); 58 vhdl->set_body (0,"variable var_EXCEPTION : Texception;"); 59 60 61 vhdl->set_body (0,"begin -- TRANSITION"); 62 vhdl->set_body (1,"if (in_CLOCK'event and in_CLOCK = '1')then"); 63 vhdl->set_body (0,""); 64 vhdl->set_comment(2,"---------------------------------------------------------------------------"); 65 vhdl->set_comment(2,"Reset"); 66 vhdl->set_comment(2,"---------------------------------------------------------------------------"); 67 vhdl->set_body (2,"if (in_NRESET = '0') then"); 68 if (_param->_size_queue>1) 69 { 70 vhdl->set_body (3,"reg_PTR_READ <= "+std_logic_cst( log2(_param->_size_queue), 0)+";"); 71 vhdl->set_body (3,"reg_PTR_WRITE <= "+std_logic_cst( log2(_param->_size_queue), 0)+";"); 72 } 73 // vhdl->set_body (3,"var_EMPTY := '1';"); 74 75 for (uint32_t i=0; i<_param->_size_queue; i++) 76 { 77 vhdl->set_body (3,"reg_STATE("+toString(i)+") <= IFETCH_QUEUE_STATE_EMPTY;"); 78 } 79 80 vhdl->set_body (3,""); 81 vhdl->set_body (2,"else"); 82 vhdl->set_body (3,""); 83 // std::string write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)"; 84 // vhdl->set_body (3,"var_STATE := reg_STATE ("+write+");"); 85 vhdl->set_body (3,"var_STATE := reg_STATE ;"); 86 if (_param->_size_queue>1) 87 { 88 vhdl->set_body (3,"var_PTR_READ := reg_PTR_READ;"); 89 vhdl->set_body (3,"var_PTR_WRITE := reg_PTR_WRITE;"); 90 } 91 92 // if (_param->_size_queue>1) 93 // { 94 // vhdl->set_body (3,"var_EMPTY := reg_EMPTY ;"); 95 // } 96 vhdl->set_body (3,"var_INSTRUCTION_ENABLE := reg_INSTRUCTION_ENABLE ;"); 97 vhdl->set_body (3,"var_ADDRESS := reg_ADDRESS ;"); 98 if(_param->_have_port_inst_ifetch_ptr) 99 vhdl->set_body (3,"var_INST_IFETCH_PTR := reg_INST_IFETCH_PTR ;"); 100 if (_param->_have_port_ifetch_queue_ptr) 101 // vhdl->set_body (3,"var_BRANCH_UPDATE_PREDICTION_ID := reg_BRANCH_UPDATE_PREDICTION_ID;"); 102 vhdl->set_body (3,"var_BRANCH_STATE := reg_BRANCH_STATE ;"); 103 vhdl->set_body (3,"var_EXCEPTION := reg_EXCEPTION ;"); 104 105 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 106 vhdl->set_comment(3,"ADDRESS "); 107 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 108 { 109 std::string reg_ptr_write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)"; 110 vhdl->set_body (3,"if ((in_ADDRESS_VAL and internal_ADDRESS_ACK) = '1') then"); 111 vhdl->set_body (3,"var_STATE ("+reg_ptr_write+") := IFETCH_QUEUE_STATE_WAIT_RSP;"); 112 for (uint32_t i=0; i<_param->_nb_instruction; i++) 113 vhdl->set_body (3,"var_INSTRUCTION_ENABLE ("+reg_ptr_write+")("+toString(i)+") := in_address_"+toString(i)+"_instruction_enable;"); 114 115 vhdl->set_body (3,"var_ADDRESS("+reg_ptr_write+") := in_ADDRESS_INSTRUCTION_ADDRESS;"); 116 if(_param->_have_port_inst_ifetch_ptr) 117 { 118 vhdl->set_body (3,"var_INST_IFETCH_PTR("+reg_ptr_write+") := in_ADDRESS_INST_IFETCH_PTR;"); 119 } 120 vhdl->set_body (3,"var_BRANCH_STATE("+reg_ptr_write+") := in_ADDRESS_BRANCH_STATE;"); 121 if(_param->_have_port_depth) 122 vhdl->set_body (3,"var_BRANCH_UPDATE_PREDICTION_ID := in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;"); 123 if (_param->_size_queue>1) 124 { 125 vhdl->set_body (3,"if (var_PTR_WRITE ="+std_logic_cst( log2(_param->_size_queue),_param->_size_queue-1)+") then"); 126 vhdl->set_body (3,"var_PTR_WRITE := "+std_logic_cst( log2(_param->_size_queue), 0)+";"); 127 vhdl->set_body (3,"else"); 128 if (_param->_size_ifetch_queue_ptr == 1) 129 vhdl->set_body (3,"var_PTR_WRITE := not var_PTR_WRITE;"); 130 else 131 vhdl->set_body (3,"var_PTR_WRITE := (var_PTR_WRITE +"+std_logic_cst( log2(_param->_size_queue),1)+");"); 132 vhdl->set_body (3,"end if;"); 133 } 134 vhdl->set_body (3,"end if;"); 135 } 136 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 137 vhdl->set_comment(3,"DECOD "); 138 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 139 140 // have_instruction_decod <= ((internal_DECOD_0_VAL and in_DECOD_0_ACK) or 141 // (internal_DECOD_1_VAL and in_DECOD_1_ACK) or 142 // (internal_DECOD_2_VAL and in_DECOD_2_ACK) or 143 // (internal_DECOD_3_VAL and in_DECOD_3_ACK)); 144 vhdl->set_body (3,"have_instruction_decod := '0';"); 145 vhdl->set_body (3,"have_instruction_enable := '0';"); 146 std::string reg_ptr_read = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_READ)"; 147 for (uint32_t i=0; i<_param->_nb_instruction; i++) 148 { 149 vhdl->set_body (3,"if ((internal_DECOD_"+toString(i)+"_VAL and in_DECOD_"+toString(i)+"_ACK) = '1') then"); 150 vhdl->set_body (4,"have_instruction_decod := '1';"); 151 vhdl->set_body (4,"var_INSTRUCTION_ENABLE ("+reg_ptr_read+")("+toString(i)+") := '0';"); 152 vhdl->set_body (3,"end if;"); 153 vhdl->set_body (4,"have_instruction_enable := have_instruction_enable or var_INSTRUCTION_ENABLE ("+reg_ptr_read+")("+toString(i)+");"); 154 } 155 vhdl->set_body (3,"if (have_instruction_decod = '1') then"); 156 vhdl->set_body (3,"if (have_instruction_enable = '0') then"); 157 vhdl->set_body (4,"var_STATE ("+reg_ptr_read+") := IFETCH_QUEUE_STATE_EMPTY;"); 158 159 if(_param->_size_queue>1) 160 { 161 vhdl->set_body (4,"if (var_PTR_READ ="+std_logic_cst( log2(_param->_size_queue),_param->_size_queue-1)+") then"); 162 vhdl->set_body (4,"var_PTR_READ := "+std_logic_cst( log2(_param->_size_queue), 0)+"; else"); 163 if (_param->_size_ifetch_queue_ptr == 1) 164 vhdl->set_body (4,"var_PTR_READ := not var_PTR_READ;"); 165 else 166 vhdl->set_body (4,"var_PTR_READ := var_PTR_READ +"+std_logic_cst( log2(_param->_size_queue),1)+";"); 167 vhdl->set_body (4,"end if;"); 168 } 169 vhdl->set_body (3,"end if;"); 170 vhdl->set_body (3,"end if;"); 171 172 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 173 vhdl->set_comment(3,"ICACHE_RSP "); 174 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 175 { std::string address; 176 if (_param->_have_port_ifetch_queue_ptr) 177 { 178 address="conv_integer(var_internal_ICACHE_RSP_PACKET_ID)"; 179 } 180 else 181 { 182 address="0"; 183 } 184 vhdl->set_body (3,"if ((in_ICACHE_RSP_VAL and internal_ICACHE_RSP_ACK)= '1') then"); 185 if (_param->_have_port_ifetch_queue_ptr) 186 { 187 vhdl->set_body(4,"var_internal_ICACHE_RSP_PACKET_ID := in_ICACHE_RSP_PACKET_ID;"); 188 } 189 for (uint32_t i=0; i<_param->_nb_instruction; i++) 190 vhdl->set_body(3,"reg_DATA("+address+")("+toString(i)+") <= in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION ;"); 191 192 vhdl->set_body(4,"if (in_ICACHE_RSP_ERROR = ICACHE_ERROR_NONE) then"); 193 vhdl->set_body(5,"var_EXCEPTION("+address+") := EXCEPTION_IFETCH_NONE;"); 194 vhdl->set_body(4,"else if (in_ICACHE_RSP_ERROR = ICACHE_ERROR_BUS_ERROR) then"); 195 vhdl->set_body(5,"var_EXCEPTION("+address+") := EXCEPTION_IFETCH_BUS_ERROR;"); 196 vhdl->set_body (4,"end if;"); 197 vhdl->set_body (4,"end if;"); 198 vhdl->set_body(4,"if (var_STATE("+address+") = IFETCH_QUEUE_STATE_WAIT_RSP) then"); 199 vhdl->set_body(5," var_STATE("+address+") := IFETCH_QUEUE_STATE_HAVE_RSP;"); 200 vhdl->set_body(4,"else if var_STATE("+address+") = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP then"); 201 vhdl->set_body(5," var_STATE("+address+") := IFETCH_QUEUE_STATE_EMPTY;"); 202 vhdl->set_body (4,"end if;"); 203 vhdl->set_body (4,"end if;"); 204 vhdl->set_body (3,"end if;"); 205 } 206 207 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 208 vhdl->set_comment(3,"EVENT_RESET"); 209 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 210 vhdl->set_body (3,"if ((in_EVENT_RESET_VAL and internal_EVENT_RESET_ACK) = '1' ) then"); 211 for (uint32_t i=0; i<_param->_size_queue; i++) { 212 vhdl->set_body(4,"if (var_STATE("+toString(i)+") = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP) then "); 213 vhdl->set_body(4,"var_STATE("+toString(i)+") := IFETCH_QUEUE_STATE_ERROR_WAIT_RSP;"); 214 vhdl->set_body(4,"else if var_STATE("+toString(i)+") = IFETCH_QUEUE_STATE_WAIT_RSP then "); 215 vhdl->set_body(4,"var_STATE("+toString(i)+") := IFETCH_QUEUE_STATE_ERROR_WAIT_RSP;"); 216 vhdl->set_body(4,"else var_STATE("+toString(i)+") := IFETCH_QUEUE_STATE_EMPTY;"); 217 if (_param->_size_queue>1) 218 vhdl->set_body(5,"var_PTR_READ := var_PTR_WRITE;"); 219 // else 220 // vhdl->set_body(5,"reg_EMPTY <= '1';"); 221 222 vhdl->set_body(4,"end if;"); 223 vhdl->set_body(4,"end if;"); 224 } 225 //vhdl->set_body (3,"end if;"); 226 vhdl->set_body (3,"end if;"); 227 228 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 229 vhdl->set_comment(3,"WRITE Register"); 230 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 231 { 232 if (_param->_size_queue>1) { 233 vhdl->set_body (3,"reg_PTR_READ <= var_PTR_READ;"); 234 vhdl->set_body (3,"reg_PTR_WRITE <= var_PTR_WRITE;"); 235 } 236 // vhdl->set_body (3,"reg_EMPTY <= var_EMPTY;"); 237 std::string reg_ptr_write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)"; 238 // vhdl->set_body (3,"reg_STATE ("+reg_ptr_write+") <= var_STATE;"); 239 vhdl->set_body (3,"reg_STATE <= var_STATE;"); 240 for (uint32_t i=0; i<_param->_nb_instruction; i++) 241 vhdl->set_body (3,"reg_INSTRUCTION_ENABLE("+reg_ptr_write+")("+toString(i)+") <= var_INSTRUCTION_ENABLE("+reg_ptr_write+")("+toString(i)+");"); 242 // vhdl->set_body (3,"reg_ADDRESS ("+reg_ptr_write+") <= var_ADDRESS;"); 243 vhdl->set_body (3,"reg_ADDRESS <= var_ADDRESS;"); 244 if(_param->_have_port_inst_ifetch_ptr) 245 // vhdl->set_body (3,"reg_INST_IFETCH_PTR ("+reg_ptr_write+") <= var_INST_IFETCH_PTR;"); 246 vhdl->set_body (3,"reg_INST_IFETCH_PTR <= var_INST_IFETCH_PTR;"); 247 // vhdl->set_body (3,"reg_BRANCH_STATE ("+reg_ptr_write+") <= var_BRANCH_STATE;"); 248 vhdl->set_body (3,"reg_BRANCH_STATE <= var_BRANCH_STATE;"); 249 if(_param->_have_port_depth) 250 vhdl->set_body (3,"reg_BRANCH_UPDATE_PREDICTION_ID("+reg_ptr_write+") <= var_BRANCH_UPDATE_PREDICTION_ID;"); 251 if (_param->_size_queue>1) 252 vhdl->set_body (3,"reg_PTR_WRITE <= var_PTR_WRITE;"); 253 254 std::string reg_ptr_read = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_READ)"; 255 for (uint32_t i=0; i<_param->_nb_instruction; i++) 256 vhdl->set_body (3,"reg_INSTRUCTION_ENABLE("+reg_ptr_read+") ("+toString(i)+") <= var_INSTRUCTION_ENABLE("+reg_ptr_read+")("+toString(i)+");"); 257 // vhdl->set_body (3,"reg_STATE("+reg_ptr_read+") <= var_STATE;"); 258 if(_param->_size_queue>1) 259 vhdl->set_body (3,"reg_PTR_READ <= var_PTR_READ ;"); 260 // vhdl->set_body (3,"internal_ICACHE_RSP_ACK <= internal_ICACHE_RSP_ACK;"); 261 if (_param->_have_port_ifetch_queue_ptr) 262 { 263 vhdl->set_body (3,"internal_ICACHE_RSP_PACKET_ID <= var_internal_ICACHE_RSP_PACKET_ID;"); 264 std::string address; 265 if (_param->_have_port_ifetch_queue_ptr) 266 address="conv_integer(var_internal_ICACHE_RSP_PACKET_ID)"; 267 else 268 address="0"; 269 // vhdl->set_body (3,"reg_EXCEPTION("+address+") <= var_EXCEPTION;"); 270 vhdl->set_body (3,"reg_EXCEPTION <= var_EXCEPTION;"); 271 } 272 } 273 vhdl->set_body (2,"end if;"); 274 vhdl->set_body (1,"end if;"); 275 vhdl->set_body (0,"end process; -- TRANSITION"); 276 277 278 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 279 vhdl->set_comment(0,"GENMOORE"); 280 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 281 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 282 vhdl->set_comment(0,"ADDRESS "); 283 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 284 { 285 std::string reg_ptr_write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)"; 286 vhdl->set_body (1,"internal_ADDRESS_ACK <= '1' WHEN (reg_STATE("+reg_ptr_write+") = IFETCH_QUEUE_STATE_EMPTY) ELSE"); 287 vhdl->set_body (1,"'0';"); 288 vhdl->set_body (1,"out_ADDRESS_ACK <= internal_ADDRESS_ACK;"); 289 if (_param->_have_port_ifetch_queue_ptr) { 290 vhdl->set_body (1,"out_ADDRESS_IFETCH_QUEUE_ID <= reg_PTR_WRITE;"); 291 } 292 } 293 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 294 vhdl->set_comment(0,"DECOD "); 295 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 296 { 297 std::string reg_ptr_read = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_READ)"; 298 vhdl->set_body (0,"internal_ack <= '1' WHEN (reg_STATE("+reg_ptr_read+") = IFETCH_QUEUE_STATE_HAVE_RSP) ELSE"); 299 vhdl->set_body (0,"'0';"); 300 for (uint32_t j=0; j<_param->_nb_instruction; j++) 301 { 302 vhdl->set_body(0,"internal_DECOD_"+toString(j)+"_VAL <= (internal_ack AND reg_INSTRUCTION_ENABLE("+reg_ptr_read+")("+toString(j)+"));"); 303 vhdl->set_body(0,"out_DECOD_"+toString(j)+"_VAL <= internal_DECOD_"+toString(j)+"_VAL;"); 304 vhdl->set_body(0,"out_DECOD_"+toString(j)+"_INSTRUCTION <= reg_DATA("+reg_ptr_read+")("+toString(j)+") ;"); 305 } 306 vhdl->set_body(0,"out_DECOD_ADDRESS <= reg_ADDRESS("+reg_ptr_read+");"); 307 if (_param->_have_port_inst_ifetch_ptr) 308 vhdl->set_body(0,"out_DECOD_INST_IFETCH_PTR <= reg_INST_IFETCH_PTR("+reg_ptr_read+");"); 309 vhdl->set_body(0,"out_DECOD_BRANCH_STATE <= reg_BRANCH_STATE("+reg_ptr_read+");"); 310 if (_param->_have_port_depth) 311 vhdl->set_body(0,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID <= reg_BRANCH_UPDATE_PREDICTION_ID("+reg_ptr_read+");"); 312 vhdl->set_body(0,"out_DECOD_EXCEPTION <= reg_EXCEPTION("+reg_ptr_read+");"); 313 } 314 vhdl->set_body(0,""); 315 26 316 log_printf(FUNC,Ifetch_queue,FUNCTION,"End"); 27 317 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_vhdl_declaration.cpp
r81 r135 23 23 { 24 24 log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); 25 26 vhdl->set_constant ("IFETCH_QUEUE_STATE_EMPTY ",IFETCH_QUEUE_STATE_SIZE,IFETCH_QUEUE_STATE_EMPTY); 27 // vhdl->set_constant ("IFETCH_QUEUE_STATE_WAIT_REQ ",IFETCH_QUEUE_STATE_SIZE,IFETCH_QUEUE_STATE_WAIT_REQ); 28 vhdl->set_constant ("IFETCH_QUEUE_STATE_WAIT_RSP ",IFETCH_QUEUE_STATE_SIZE,IFETCH_QUEUE_STATE_WAIT_RSP); 29 vhdl->set_constant ("IFETCH_QUEUE_STATE_HAVE_RSP ",IFETCH_QUEUE_STATE_SIZE,IFETCH_QUEUE_STATE_HAVE_RSP); 30 vhdl->set_constant ("IFETCH_QUEUE_STATE_ERROR_WAIT_RSP ",IFETCH_QUEUE_STATE_SIZE,IFETCH_QUEUE_STATE_ERROR_WAIT_RSP); 31 32 vhdl->set_constant ("EXCEPTION_IFETCH_NONE ",_param->_size_exception_ifetch,EXCEPTION_IFETCH_NONE); 33 vhdl->set_constant ("EXCEPTION_IFETCH_BUS_ERROR ",_param->_size_exception_ifetch,EXCEPTION_IFETCH_BUS_ERROR); 34 35 vhdl->set_constant ("ICACHE_ERROR_NONE ",_param->_size_icache_error,ICACHE_ERROR_NONE); 36 vhdl->set_constant ("ICACHE_ERROR_BUS_ERROR ",_param->_size_icache_error,ICACHE_ERROR_BUS_ERROR); 37 38 if (_param->_size_queue>1) 39 { 40 vhdl->set_signal ("reg_PTR_READ ", log2(_param->_size_queue)); 41 vhdl->set_signal ("reg_PTR_WRITE ", log2(_param->_size_queue)); 42 } 43 if (_param->_have_port_ifetch_queue_ptr) 44 { 45 if (_param->_size_queue>1) 46 vhdl->set_signal ("reg_PACKET_PTR ", log2(_param->_size_queue)); 47 else 48 vhdl->set_signal ("reg_PACKET_PTR ", 1); 49 } 50 51 vhdl->set_signal ("reg_EMPTY ", 1); 52 53 vhdl->set_type ("Tcase ","array ("+toString(_param->_nb_instruction-1)+" downto 0) of "+std_logic(_param->_size_instruction)); 54 vhdl->set_type ("Tcase_enable ","array ("+toString(_param->_nb_instruction-1)+" downto 0) of std_logic"); 55 56 vhdl->set_type ("Tstate ","array ("+toString(_param->_size_queue-1)+" downto 0) of "+std_logic(IFETCH_QUEUE_STATE_SIZE)); 57 vhdl->set_signal ("reg_STATE ", "Tstate"); 58 59 vhdl->set_type ("Tqueue ","array ("+toString(_param->_size_queue-1)+" downto 0) of Tcase"); 60 vhdl->set_signal ("reg_DATA ", "Tqueue"); 61 62 vhdl->set_type ("Tenable ","array ("+toString(_param->_size_queue-1)+" downto 0) of Tcase_enable"); 63 vhdl->set_signal ("reg_INSTRUCTION_ENABLE ", "Tenable"); 64 vhdl->set_type ("Tadress ","array ("+toString(_param->_size_queue-1)+" downto 0) of "+std_logic(_param->_size_instruction)); 65 vhdl->set_signal ("reg_ADDRESS ", "Tadress"); 66 67 if (_param->_have_port_inst_ifetch_ptr) 68 { 69 vhdl->set_type ("Tinst_ptr ","array ("+toString(_param->_size_queue-1)+" downto 0) of "+std_logic(_param->_size_inst_ifetch_ptr)); 70 vhdl->set_signal ("reg_INST_IFETCH_PTR ", "Tinst_ptr"); 71 } 72 if (_param->_have_port_depth) 73 { 74 vhdl->set_type ("Tbranch ","array ("+toString(_param->_size_queue-1)+" downto 0) of "+std_logic(_param->_size_depth)); 75 vhdl->set_signal ("reg_BRANCH_UPDATE_PREDICTION_ID ", "Tbranch"); 76 } 77 vhdl->set_type ("Tbranch_state ","array ("+toString(_param->_size_queue-1)+" downto 0) of "+std_logic(_param->_size_branch_state)); 78 vhdl->set_signal ("reg_BRANCH_STATE ", "Tbranch_state"); 79 vhdl->set_type ("Texception ","array ("+toString(_param->_size_queue-1)+" downto 0) of "+std_logic(_param->_size_exception_ifetch)); 80 vhdl->set_signal ("reg_EXCEPTION ", "Texception"); 81 82 for (uint32_t i=0; i<_param->_nb_instruction; ++i) 83 vhdl->set_signal ("internal_DECOD_"+toString(i)+"_VAL ", 1); 84 vhdl->set_signal ("internal_ADDRESS_ACK ", 1); 85 vhdl->set_signal ("internal_ICACHE_RSP_ACK ", 1); 86 vhdl->set_signal ("internal_EVENT_RESET_ACK ", 1); 87 if(_param->_have_port_ifetch_queue_ptr) 88 vhdl->set_signal ("internal_ICACHE_RSP_PACKET_ID ", _param->_size_ifetch_queue_ptr); 89 vhdl->set_signal ("internal_ack ", 1); 90 25 91 log_printf(FUNC,Ifetch_queue,FUNCTION,"End"); 26 92 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp
r109 r135 38 38 { 39 39 _size_instruction_address = size_general_data; 40 _size_ifetch_queue_ptr = log2( size_queue);40 _size_ifetch_queue_ptr = log2(_size_queue); 41 41 _size_inst_ifetch_ptr = log2(nb_instruction); 42 42 _size_depth = size_branch_update_prediction;
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