Ignore:
Timestamp:
May 12, 2010, 7:34:01 PM (14 years ago)
Author:
rosiere
Message:

1) add counters_t type for interface
2) fix in check load in load_store_unit
3) add parameters (but not yet implemented)
4) change environment and add script (distcc_env.sh ...)
5) add warning if an unser change rename flag with l.mtspr instruction
6) ...

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h

    r131 r138  
    5050  public    : Stat                           * _stat;
    5151   
    52   private   : counter_t                      * _stat_nb_read;
    53   private   : counter_t                      * _stat_nb_write;
     52  // private   : counter_t                      * _stat_nb_read;
     53  // private   : counter_t                      * _stat_nb_write;
     54  private   : counters_t                     * _stat_port_read;
     55  private   : counters_t                     * _stat_port_write;
     56  private   : counters_t                     * _stat_port_read_write;
    5457#endif
    5558

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_statistics_declaration.cpp

    r84 r138  
    2121                      param_statistics);
    2222
    23     _stat_nb_read           = _stat->create_variable("nb_read" );
    24     _stat_nb_write          = _stat->create_variable("nb_write");
     23    if (_param->_nb_port_read>0)
     24    _stat_port_read         = _stat->create_counters("port_read",_param->_nb_port_read,"",
     25                                                     _("Usage of read port %d."),
     26                                                     _("Percent of usage read port %d."),
     27                                                     _("Average of usage read port.")
     28                                                     );
    2529
    26     _stat->create_expr_average_by_cycle("average_read" , "nb_read" , "", _("Average read by cycle" ));
    27     _stat->create_expr_average_by_cycle("average_write", "nb_write", "", _("Average write by cycle"));
     30    if (_param->_nb_port_write>0)
     31    _stat_port_write        = _stat->create_counters("port_write",_param->_nb_port_write,"",
     32                                                     _("Usage of write port %d."),
     33                                                     _("Percent of usage write port %d."),
     34                                                     _("Average of usage write port.")
     35                                                     );
     36    if (_param->_nb_port_read_write>0)
     37    _stat_port_read_write   = _stat->create_counters("port_read_write",_param->_nb_port_read_write,"",
     38                                                     _("Usage of read_write port."),
     39                                                     _("Percent of usage read_write port %d."),
     40                                                     _("Average of usage read_write port.")
     41                                                     );
    2842
    29     _stat->create_expr_percent         ("percent_use_read" , "average_read" , toString(_param->_nb_port_read +_param->_nb_port_read_write), _("Percent read by cycle" ));
    30     _stat->create_expr_percent         ("percent_use_write", "average_write", toString(_param->_nb_port_write+_param->_nb_port_read_write), _("Percent write by cycle"));
     43    // _stat_nb_read           = _stat->create_variable("nb_read" );
     44    // _stat_nb_write          = _stat->create_variable("nb_write");
     45
     46    // _stat->create_expr_average_by_cycle("average_read" , "nb_read" , "", _("Average read by cycle" ));
     47    // _stat->create_expr_average_by_cycle("average_write", "nb_write", "", _("Average write by cycle"));
     48
     49    // _stat->create_expr_percent         ("percent_use_read" , "average_read" , toString(_param->_nb_port_read +_param->_nb_port_read_write), _("Percent read by cycle" ));
     50    // _stat->create_expr_percent         ("percent_use_write", "average_write", toString(_param->_nb_port_write+_param->_nb_port_read_write), _("Percent write by cycle"));
    3151
    3252  };

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp

    r131 r138  
    3737    else
    3838      {
     39#ifdef STATISTICS
     40        uint32_t stat_nb_read      =0;
     41        uint32_t stat_nb_write     =0;
     42        uint32_t stat_nb_read_write=0;
     43#endif
    3944        for (uint32_t i=0; i<_param->_nb_port_write; i++)
    4045          {
    … …  
    4550              {
    4651#ifdef STATISTICS
    47                 if (usage_is_set(_usage,USE_STATISTICS))
    48                   (*_stat_nb_write) ++;
    49 #endif   
     52                stat_nb_write++;
     53#endif
     54
     55// #ifdef STATISTICS
     56//                 if (usage_is_set(_usage,USE_STATISTICS))
     57//                   (*_stat_nb_write) ++;
     58// #endif   
    5059
    5160                Taddress_t address = (_param->_have_port_address)?PORT_READ(in_WRITE_ADDRESS[i]):0;
    … …  
    7483            if (PORT_READ(in_READ_WRITE_VAL[i]) == true)
    7584              {
     85#ifdef STATISTICS
     86                stat_nb_read_write++;
     87#endif
     88
    7689                if (PORT_READ(in_READ_WRITE_RW [i]) == RW_WRITE)
    7790                  {
    78 #ifdef STATISTICS
    79                     if (usage_is_set(_usage,USE_STATISTICS))
    80                       (*_stat_nb_write) ++;
    81 #endif   
     91// #ifdef STATISTICS
     92//                     if (usage_is_set(_usage,USE_STATISTICS))
     93//                       (*_stat_nb_write) ++;
     94// #endif   
    8295                   
    8396                    Taddress_t address = (_param->_have_port_address)?PORT_READ(in_READ_WRITE_ADDRESS[i]):0;
    … …  
    95108                    reg_DATA[address] = data;
    96109                  }
    97 #ifdef STATISTICS
    98                 else
    99                   {
    100                     if (usage_is_set(_usage,USE_STATISTICS))
    101                       (*_stat_nb_read) ++;
    102                   }
    103 #endif   
     110// #ifdef STATISTICS
     111//                 else
     112//                   {
     113//                     if (usage_is_set(_usage,USE_STATISTICS))
     114//                       (*_stat_nb_read) ++;
     115//                   }
     116// #endif   
    104117              }
    105118          }
     119
     120       
     121#ifdef STATISTICS
     122        if (usage_is_set(_usage,USE_STATISTICS))
     123          {
     124            for (uint32_t i=0; i<_param->_nb_port_read; i++)
     125              if ( PORT_READ(in_READ_VAL [i]) == 1)
     126                {
     127                  stat_nb_read ++;
     128                  // (*_stat_nb_read) ++;
     129                }
     130
     131            if (_param->_nb_port_read>0)
     132            (*_stat_port_read      ) += stat_nb_read;
     133            if (_param->_nb_port_write>0)
     134            (*_stat_port_write     ) += stat_nb_write;
     135            if (_param->_nb_port_read_write>0)
     136            (*_stat_port_read_write) += stat_nb_read_write;
     137          }
     138#endif   
    106139      }
    107 
    108 #ifdef STATISTICS
    109     if (usage_is_set(_usage,USE_STATISTICS))
    110       for (uint32_t i=0; i<_param->_nb_port_read; i++)
    111         if ( PORT_READ(in_READ_VAL [i]) == 1)
    112           (*_stat_nb_read) ++;
    113 #endif   
    114140
    115141#if defined(DEBUG_RegisterFile_Monolithic) and DEBUG_RegisterFile_Monolithic and (DEBUG >= DEBUG_TRACE)

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info

    r137 r138  
    33target_dep      all     RegisterFile_Multi_Banked_00.ngc
    44target_dep      RegisterFile_Multi_Banked_00.ngc        RegisterFile_Multi_Banked_00.prj
    5 target_dep      RegisterFile_Multi_Banked_00.prj        RegisterFile_Multi_Banked_00_bank_Pack.vhdl RegisterFile_Multi_Banked_00_bank.vhdl RegisterFile_Multi_Banked_00_Pack.vhdl RegisterFile_Multi_Banked_00_select_12_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_12_ports.vhdl RegisterFile_Multi_Banked_00_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_6_ports.vhdl RegisterFile_Multi_Banked_00.vhdl
     5target_dep      RegisterFile_Multi_Banked_00.prj        RegisterFile_Multi_Banked_00_bank_Pack.vhdl RegisterFile_Multi_Banked_00_bank.vhdl RegisterFile_Multi_Banked_00_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports.vhdl RegisterFile_Multi_Banked_00.vhdl
    66
    77# RegisterFile_Multi_Banked_01
    88target_dep      all     RegisterFile_Multi_Banked_01.ngc
    99target_dep      RegisterFile_Multi_Banked_01.ngc        RegisterFile_Multi_Banked_01.prj
    10 target_dep      RegisterFile_Multi_Banked_01.prj        RegisterFile_Multi_Banked_01_bank_Pack.vhdl RegisterFile_Multi_Banked_01_bank.vhdl RegisterFile_Multi_Banked_01_Pack.vhdl RegisterFile_Multi_Banked_01_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_01_select_6_ports.vhdl RegisterFile_Multi_Banked_01.vhdl
     10target_dep      RegisterFile_Multi_Banked_01.prj        RegisterFile_Multi_Banked_01_bank_Pack.vhdl RegisterFile_Multi_Banked_01_bank.vhdl RegisterFile_Multi_Banked_01_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports.vhdl RegisterFile_Multi_Banked_01.vhdl
    1111
    1212# RegisterFile_Multi_Banked_02
    1313target_dep      all     RegisterFile_Multi_Banked_02.ngc
    1414target_dep      RegisterFile_Multi_Banked_02.ngc        RegisterFile_Multi_Banked_02.prj
    15 target_dep      RegisterFile_Multi_Banked_02.prj        RegisterFile_Multi_Banked_02_bank_Pack.vhdl RegisterFile_Multi_Banked_02_bank.vhdl RegisterFile_Multi_Banked_02_Pack.vhdl RegisterFile_Multi_Banked_02_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_1_ports.vhdl RegisterFile_Multi_Banked_02_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_2_ports.vhdl RegisterFile_Multi_Banked_02.vhdl
     15target_dep      RegisterFile_Multi_Banked_02.prj        RegisterFile_Multi_Banked_02_bank_Pack.vhdl RegisterFile_Multi_Banked_02_bank.vhdl RegisterFile_Multi_Banked_02_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports.vhdl RegisterFile_Multi_Banked_02.vhdl
    1616
    1717# RegisterFile_Multi_Banked_03
    1818target_dep      all     RegisterFile_Multi_Banked_03.ngc
    1919target_dep      RegisterFile_Multi_Banked_03.ngc        RegisterFile_Multi_Banked_03.prj
    20 target_dep      RegisterFile_Multi_Banked_03.prj        RegisterFile_Multi_Banked_03_bank_Pack.vhdl RegisterFile_Multi_Banked_03_bank.vhdl RegisterFile_Multi_Banked_03_Pack.vhdl RegisterFile_Multi_Banked_03_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_03_select_2_ports.vhdl RegisterFile_Multi_Banked_03.vhdl
     20target_dep      RegisterFile_Multi_Banked_03.prj        RegisterFile_Multi_Banked_03_bank_Pack.vhdl RegisterFile_Multi_Banked_03_bank.vhdl RegisterFile_Multi_Banked_03_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports.vhdl RegisterFile_Multi_Banked_03.vhdl
    2121
    2222# RegisterFile_Multi_Banked_04
    2323target_dep      all     RegisterFile_Multi_Banked_04.ngc
    2424target_dep      RegisterFile_Multi_Banked_04.ngc        RegisterFile_Multi_Banked_04.prj
    25 target_dep      RegisterFile_Multi_Banked_04.prj        RegisterFile_Multi_Banked_04_bank_Pack.vhdl RegisterFile_Multi_Banked_04_bank.vhdl RegisterFile_Multi_Banked_04_Pack.vhdl RegisterFile_Multi_Banked_04_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_1_ports.vhdl RegisterFile_Multi_Banked_04_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_2_ports.vhdl RegisterFile_Multi_Banked_04.vhdl
     25target_dep      RegisterFile_Multi_Banked_04.prj        RegisterFile_Multi_Banked_04_bank_Pack.vhdl RegisterFile_Multi_Banked_04_bank.vhdl RegisterFile_Multi_Banked_04_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports.vhdl RegisterFile_Multi_Banked_04.vhdl
    2626
    2727# RegisterFile_Multi_Banked_05
    2828target_dep      all     RegisterFile_Multi_Banked_05.ngc
    2929target_dep      RegisterFile_Multi_Banked_05.ngc        RegisterFile_Multi_Banked_05.prj
    30 target_dep      RegisterFile_Multi_Banked_05.prj        RegisterFile_Multi_Banked_05_bank_Pack.vhdl RegisterFile_Multi_Banked_05_bank.vhdl RegisterFile_Multi_Banked_05_Pack.vhdl RegisterFile_Multi_Banked_05_select_12_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_12_ports.vhdl RegisterFile_Multi_Banked_05_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_6_ports.vhdl RegisterFile_Multi_Banked_05.vhdl
     30target_dep      RegisterFile_Multi_Banked_05.prj        RegisterFile_Multi_Banked_05_bank_Pack.vhdl RegisterFile_Multi_Banked_05_bank.vhdl RegisterFile_Multi_Banked_05_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports.vhdl RegisterFile_Multi_Banked_05.vhdl
    3131
    3232# RegisterFile_Multi_Banked_06
    3333target_dep      all     RegisterFile_Multi_Banked_06.ngc
    3434target_dep      RegisterFile_Multi_Banked_06.ngc        RegisterFile_Multi_Banked_06.prj
    35 target_dep      RegisterFile_Multi_Banked_06.prj        RegisterFile_Multi_Banked_06_bank_Pack.vhdl RegisterFile_Multi_Banked_06_bank.vhdl RegisterFile_Multi_Banked_06_Pack.vhdl RegisterFile_Multi_Banked_06_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_06_select_3_ports.vhdl RegisterFile_Multi_Banked_06.vhdl
     35target_dep      RegisterFile_Multi_Banked_06.prj        RegisterFile_Multi_Banked_06_bank_Pack.vhdl RegisterFile_Multi_Banked_06_bank.vhdl RegisterFile_Multi_Banked_06_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports.vhdl RegisterFile_Multi_Banked_06.vhdl
    3636
    3737# RegisterFile_Multi_Banked_07
    3838target_dep      all     RegisterFile_Multi_Banked_07.ngc
    3939target_dep      RegisterFile_Multi_Banked_07.ngc        RegisterFile_Multi_Banked_07.prj
    40 target_dep      RegisterFile_Multi_Banked_07.prj        RegisterFile_Multi_Banked_07_bank_Pack.vhdl RegisterFile_Multi_Banked_07_bank.vhdl RegisterFile_Multi_Banked_07_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports.vhdl RegisterFile_Multi_Banked_07.vhdl
     40target_dep      RegisterFile_Multi_Banked_07.prj        RegisterFile_Multi_Banked_07_bank_Pack.vhdl RegisterFile_Multi_Banked_07_bank.vhdl RegisterFile_Multi_Banked_07_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports.vhdl RegisterFile_Multi_Banked_07_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports.vhdl RegisterFile_Multi_Banked_07.vhdl
    4141
    4242# RegisterFile_Multi_Banked_08
    4343target_dep      all     RegisterFile_Multi_Banked_08.ngc
    4444target_dep      RegisterFile_Multi_Banked_08.ngc        RegisterFile_Multi_Banked_08.prj
    45 target_dep      RegisterFile_Multi_Banked_08.prj        RegisterFile_Multi_Banked_08_bank_Pack.vhdl RegisterFile_Multi_Banked_08_bank.vhdl RegisterFile_Multi_Banked_08_Pack.vhdl RegisterFile_Multi_Banked_08_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_1_ports.vhdl RegisterFile_Multi_Banked_08_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_2_ports.vhdl RegisterFile_Multi_Banked_08.vhdl
     45target_dep      RegisterFile_Multi_Banked_08.prj        RegisterFile_Multi_Banked_08_bank_Pack.vhdl RegisterFile_Multi_Banked_08_bank.vhdl RegisterFile_Multi_Banked_08_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports.vhdl RegisterFile_Multi_Banked_08_select_22_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_22_ports.vhdl RegisterFile_Multi_Banked_08.vhdl
    4646
    4747# RegisterFile_Multi_Banked_09
    4848target_dep      all     RegisterFile_Multi_Banked_09.ngc
    4949target_dep      RegisterFile_Multi_Banked_09.ngc        RegisterFile_Multi_Banked_09.prj
    50 target_dep      RegisterFile_Multi_Banked_09.prj        RegisterFile_Multi_Banked_09_bank_Pack.vhdl RegisterFile_Multi_Banked_09_bank.vhdl RegisterFile_Multi_Banked_09_Pack.vhdl RegisterFile_Multi_Banked_09_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_6_ports.vhdl RegisterFile_Multi_Banked_09.vhdl
     50target_dep      RegisterFile_Multi_Banked_09.prj        RegisterFile_Multi_Banked_09_bank_Pack.vhdl RegisterFile_Multi_Banked_09_bank.vhdl RegisterFile_Multi_Banked_09_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports.vhdl RegisterFile_Multi_Banked_09_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_3_ports.vhdl RegisterFile_Multi_Banked_09_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_4_ports.vhdl RegisterFile_Multi_Banked_09.vhdl
    5151
    5252# RegisterFile_Multi_Banked_10
    5353target_dep      all     RegisterFile_Multi_Banked_10.ngc
    5454target_dep      RegisterFile_Multi_Banked_10.ngc        RegisterFile_Multi_Banked_10.prj
    55 target_dep      RegisterFile_Multi_Banked_10.prj        RegisterFile_Multi_Banked_10_bank_Pack.vhdl RegisterFile_Multi_Banked_10_bank.vhdl RegisterFile_Multi_Banked_10_Pack.vhdl RegisterFile_Multi_Banked_10_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_10_select_3_ports.vhdl RegisterFile_Multi_Banked_10.vhdl
     55target_dep      RegisterFile_Multi_Banked_10.prj        RegisterFile_Multi_Banked_10_bank_Pack.vhdl RegisterFile_Multi_Banked_10_bank.vhdl RegisterFile_Multi_Banked_10_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports.vhdl RegisterFile_Multi_Banked_10.vhdl
    5656
     57# RegisterFile_Multi_Banked_11
     58target_dep      all     RegisterFile_Multi_Banked_11.ngc
     59target_dep      RegisterFile_Multi_Banked_11.ngc        RegisterFile_Multi_Banked_11.prj
     60target_dep      RegisterFile_Multi_Banked_11.prj        RegisterFile_Multi_Banked_11_bank_Pack.vhdl RegisterFile_Multi_Banked_11_bank.vhdl RegisterFile_Multi_Banked_11_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports.vhdl RegisterFile_Multi_Banked_11_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_2_ports.vhdl RegisterFile_Multi_Banked_11.vhdl
     61
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