Changeset 139 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic

Timestamp:

Jul 30, 2010, 4:47:27 PM (14 years ago)

Author:

rosiere

Message:

• Add test for all configuration
• RAT : add rat scheme (depth_save)

Location:

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile

Files:

• RegisterFile_Monolithic/SelfTest/mkf.info (modified) (1 diff)
• RegisterFile_Multi_Banked/SelfTest/mkf.info (modified) (1 diff)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info

@@ -5 +5 @@
 target_dep      RegisterFile_Monolithic_0.prj   RegisterFile_Monolithic_0_Pack.vhdl RegisterFile_Monolithic_0.vhdl
 
-# RegisterFile_Monolithic_1
-target_dep      all     RegisterFile_Monolithic_1.ngc
-target_dep      RegisterFile_Monolithic_1.ngc   RegisterFile_Monolithic_1.prj
-target_dep      RegisterFile_Monolithic_1.prj   RegisterFile_Monolithic_1_Pack.vhdl RegisterFile_Monolithic_1.vhdl
-

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info

@@ -1 +1 @@
 
-# RegisterFile_Multi_Banked_00
-target_dep      all     RegisterFile_Multi_Banked_00.ngc
-target_dep      RegisterFile_Multi_Banked_00.ngc        RegisterFile_Multi_Banked_00.prj
-target_dep      RegisterFile_Multi_Banked_00.prj        RegisterFile_Multi_Banked_00_bank_Pack.vhdl RegisterFile_Multi_Banked_00_bank.vhdl RegisterFile_Multi_Banked_00_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports.vhdl RegisterFile_Multi_Banked_00.vhdl
+# RegisterFile_Multi_Banked_0
+target_dep      all     RegisterFile_Multi_Banked_0.ngc
+target_dep      RegisterFile_Multi_Banked_0.ngc RegisterFile_Multi_Banked_0.prj
+target_dep      RegisterFile_Multi_Banked_0.prj RegisterFile_Multi_Banked_0_bank_Pack.vhdl RegisterFile_Multi_Banked_0_bank.vhdl RegisterFile_Multi_Banked_0_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports.vhdl RegisterFile_Multi_Banked_0_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_2_ports.vhdl RegisterFile_Multi_Banked_0.vhdl
 
-# RegisterFile_Multi_Banked_01
-target_dep      all     RegisterFile_Multi_Banked_01.ngc
-target_dep      RegisterFile_Multi_Banked_01.ngc        RegisterFile_Multi_Banked_01.prj
-target_dep      RegisterFile_Multi_Banked_01.prj        RegisterFile_Multi_Banked_01_bank_Pack.vhdl RegisterFile_Multi_Banked_01_bank.vhdl RegisterFile_Multi_Banked_01_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports.vhdl RegisterFile_Multi_Banked_01.vhdl
+# RegisterFile_Multi_Banked_1
+target_dep      all     RegisterFile_Multi_Banked_1.ngc
+target_dep      RegisterFile_Multi_Banked_1.ngc RegisterFile_Multi_Banked_1.prj
+target_dep      RegisterFile_Multi_Banked_1.prj RegisterFile_Multi_Banked_1_bank_Pack.vhdl RegisterFile_Multi_Banked_1_bank.vhdl RegisterFile_Multi_Banked_1_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports.vhdl RegisterFile_Multi_Banked_1_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_2_ports.vhdl RegisterFile_Multi_Banked_1.vhdl
 
-# RegisterFile_Multi_Banked_02
-target_dep      all     RegisterFile_Multi_Banked_02.ngc
-target_dep      RegisterFile_Multi_Banked_02.ngc        RegisterFile_Multi_Banked_02.prj
-target_dep      RegisterFile_Multi_Banked_02.prj        RegisterFile_Multi_Banked_02_bank_Pack.vhdl RegisterFile_Multi_Banked_02_bank.vhdl RegisterFile_Multi_Banked_02_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports.vhdl RegisterFile_Multi_Banked_02.vhdl
-
-# RegisterFile_Multi_Banked_03
-target_dep      all     RegisterFile_Multi_Banked_03.ngc
-target_dep      RegisterFile_Multi_Banked_03.ngc        RegisterFile_Multi_Banked_03.prj
-target_dep      RegisterFile_Multi_Banked_03.prj        RegisterFile_Multi_Banked_03_bank_Pack.vhdl RegisterFile_Multi_Banked_03_bank.vhdl RegisterFile_Multi_Banked_03_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports.vhdl RegisterFile_Multi_Banked_03.vhdl
-
-# RegisterFile_Multi_Banked_04
-target_dep      all     RegisterFile_Multi_Banked_04.ngc
-target_dep      RegisterFile_Multi_Banked_04.ngc        RegisterFile_Multi_Banked_04.prj
-target_dep      RegisterFile_Multi_Banked_04.prj        RegisterFile_Multi_Banked_04_bank_Pack.vhdl RegisterFile_Multi_Banked_04_bank.vhdl RegisterFile_Multi_Banked_04_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports.vhdl RegisterFile_Multi_Banked_04.vhdl
-
-# RegisterFile_Multi_Banked_05
-target_dep      all     RegisterFile_Multi_Banked_05.ngc
-target_dep      RegisterFile_Multi_Banked_05.ngc        RegisterFile_Multi_Banked_05.prj
-target_dep      RegisterFile_Multi_Banked_05.prj        RegisterFile_Multi_Banked_05_bank_Pack.vhdl RegisterFile_Multi_Banked_05_bank.vhdl RegisterFile_Multi_Banked_05_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports.vhdl RegisterFile_Multi_Banked_05.vhdl
-
-# RegisterFile_Multi_Banked_06
-target_dep      all     RegisterFile_Multi_Banked_06.ngc
-target_dep      RegisterFile_Multi_Banked_06.ngc        RegisterFile_Multi_Banked_06.prj
-target_dep      RegisterFile_Multi_Banked_06.prj        RegisterFile_Multi_Banked_06_bank_Pack.vhdl RegisterFile_Multi_Banked_06_bank.vhdl RegisterFile_Multi_Banked_06_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports.vhdl RegisterFile_Multi_Banked_06.vhdl
-
-# RegisterFile_Multi_Banked_07
-target_dep      all     RegisterFile_Multi_Banked_07.ngc
-target_dep      RegisterFile_Multi_Banked_07.ngc        RegisterFile_Multi_Banked_07.prj
-target_dep      RegisterFile_Multi_Banked_07.prj        RegisterFile_Multi_Banked_07_bank_Pack.vhdl RegisterFile_Multi_Banked_07_bank.vhdl RegisterFile_Multi_Banked_07_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports.vhdl RegisterFile_Multi_Banked_07_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports.vhdl RegisterFile_Multi_Banked_07.vhdl
-
-# RegisterFile_Multi_Banked_08
-target_dep      all     RegisterFile_Multi_Banked_08.ngc
-target_dep      RegisterFile_Multi_Banked_08.ngc        RegisterFile_Multi_Banked_08.prj
-target_dep      RegisterFile_Multi_Banked_08.prj        RegisterFile_Multi_Banked_08_bank_Pack.vhdl RegisterFile_Multi_Banked_08_bank.vhdl RegisterFile_Multi_Banked_08_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports.vhdl RegisterFile_Multi_Banked_08_select_22_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_22_ports.vhdl RegisterFile_Multi_Banked_08.vhdl
-
-# RegisterFile_Multi_Banked_09
-target_dep      all     RegisterFile_Multi_Banked_09.ngc
-target_dep      RegisterFile_Multi_Banked_09.ngc        RegisterFile_Multi_Banked_09.prj
-target_dep      RegisterFile_Multi_Banked_09.prj        RegisterFile_Multi_Banked_09_bank_Pack.vhdl RegisterFile_Multi_Banked_09_bank.vhdl RegisterFile_Multi_Banked_09_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports.vhdl RegisterFile_Multi_Banked_09_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_3_ports.vhdl RegisterFile_Multi_Banked_09_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_4_ports.vhdl RegisterFile_Multi_Banked_09.vhdl
-
-# RegisterFile_Multi_Banked_10
-target_dep      all     RegisterFile_Multi_Banked_10.ngc
-target_dep      RegisterFile_Multi_Banked_10.ngc        RegisterFile_Multi_Banked_10.prj
-target_dep      RegisterFile_Multi_Banked_10.prj        RegisterFile_Multi_Banked_10_bank_Pack.vhdl RegisterFile_Multi_Banked_10_bank.vhdl RegisterFile_Multi_Banked_10_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports.vhdl RegisterFile_Multi_Banked_10.vhdl
-
-# RegisterFile_Multi_Banked_11
-target_dep      all     RegisterFile_Multi_Banked_11.ngc
-target_dep      RegisterFile_Multi_Banked_11.ngc        RegisterFile_Multi_Banked_11.prj
-target_dep      RegisterFile_Multi_Banked_11.prj        RegisterFile_Multi_Banked_11_bank_Pack.vhdl RegisterFile_Multi_Banked_11_bank.vhdl RegisterFile_Multi_Banked_11_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports.vhdl RegisterFile_Multi_Banked_11_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_2_ports.vhdl RegisterFile_Multi_Banked_11.vhdl
-