Ignore:
Timestamp:
Jul 30, 2010, 4:47:27 PM (14 years ago)
Author:
rosiere
Message:
  • Add test for all configuration
  • RAT : add rat scheme (depth_save)
Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info

    r137 r139  
    55target_dep      RegisterFile_Monolithic_0.prj   RegisterFile_Monolithic_0_Pack.vhdl RegisterFile_Monolithic_0.vhdl
    66
    7 # RegisterFile_Monolithic_1
    8 target_dep      all     RegisterFile_Monolithic_1.ngc
    9 target_dep      RegisterFile_Monolithic_1.ngc   RegisterFile_Monolithic_1.prj
    10 target_dep      RegisterFile_Monolithic_1.prj   RegisterFile_Monolithic_1_Pack.vhdl RegisterFile_Monolithic_1.vhdl
    11 
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info

    r138 r139  
    11
    2 # RegisterFile_Multi_Banked_00
    3 target_dep      all     RegisterFile_Multi_Banked_00.ngc
    4 target_dep      RegisterFile_Multi_Banked_00.ngc        RegisterFile_Multi_Banked_00.prj
    5 target_dep      RegisterFile_Multi_Banked_00.prj        RegisterFile_Multi_Banked_00_bank_Pack.vhdl RegisterFile_Multi_Banked_00_bank.vhdl RegisterFile_Multi_Banked_00_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports.vhdl RegisterFile_Multi_Banked_00.vhdl
     2# RegisterFile_Multi_Banked_0
     3target_dep      all     RegisterFile_Multi_Banked_0.ngc
     4target_dep      RegisterFile_Multi_Banked_0.ngc RegisterFile_Multi_Banked_0.prj
     5target_dep      RegisterFile_Multi_Banked_0.prj RegisterFile_Multi_Banked_0_bank_Pack.vhdl RegisterFile_Multi_Banked_0_bank.vhdl RegisterFile_Multi_Banked_0_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports.vhdl RegisterFile_Multi_Banked_0_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_2_ports.vhdl RegisterFile_Multi_Banked_0.vhdl
    66
    7 # RegisterFile_Multi_Banked_01
    8 target_dep      all     RegisterFile_Multi_Banked_01.ngc
    9 target_dep      RegisterFile_Multi_Banked_01.ngc        RegisterFile_Multi_Banked_01.prj
    10 target_dep      RegisterFile_Multi_Banked_01.prj        RegisterFile_Multi_Banked_01_bank_Pack.vhdl RegisterFile_Multi_Banked_01_bank.vhdl RegisterFile_Multi_Banked_01_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports.vhdl RegisterFile_Multi_Banked_01.vhdl
     7# RegisterFile_Multi_Banked_1
     8target_dep      all     RegisterFile_Multi_Banked_1.ngc
     9target_dep      RegisterFile_Multi_Banked_1.ngc RegisterFile_Multi_Banked_1.prj
     10target_dep      RegisterFile_Multi_Banked_1.prj RegisterFile_Multi_Banked_1_bank_Pack.vhdl RegisterFile_Multi_Banked_1_bank.vhdl RegisterFile_Multi_Banked_1_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports.vhdl RegisterFile_Multi_Banked_1_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_2_ports.vhdl RegisterFile_Multi_Banked_1.vhdl
    1111
    12 # RegisterFile_Multi_Banked_02
    13 target_dep      all     RegisterFile_Multi_Banked_02.ngc
    14 target_dep      RegisterFile_Multi_Banked_02.ngc        RegisterFile_Multi_Banked_02.prj
    15 target_dep      RegisterFile_Multi_Banked_02.prj        RegisterFile_Multi_Banked_02_bank_Pack.vhdl RegisterFile_Multi_Banked_02_bank.vhdl RegisterFile_Multi_Banked_02_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports.vhdl RegisterFile_Multi_Banked_02.vhdl
    16 
    17 # RegisterFile_Multi_Banked_03
    18 target_dep      all     RegisterFile_Multi_Banked_03.ngc
    19 target_dep      RegisterFile_Multi_Banked_03.ngc        RegisterFile_Multi_Banked_03.prj
    20 target_dep      RegisterFile_Multi_Banked_03.prj        RegisterFile_Multi_Banked_03_bank_Pack.vhdl RegisterFile_Multi_Banked_03_bank.vhdl RegisterFile_Multi_Banked_03_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports.vhdl RegisterFile_Multi_Banked_03.vhdl
    21 
    22 # RegisterFile_Multi_Banked_04
    23 target_dep      all     RegisterFile_Multi_Banked_04.ngc
    24 target_dep      RegisterFile_Multi_Banked_04.ngc        RegisterFile_Multi_Banked_04.prj
    25 target_dep      RegisterFile_Multi_Banked_04.prj        RegisterFile_Multi_Banked_04_bank_Pack.vhdl RegisterFile_Multi_Banked_04_bank.vhdl RegisterFile_Multi_Banked_04_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports.vhdl RegisterFile_Multi_Banked_04.vhdl
    26 
    27 # RegisterFile_Multi_Banked_05
    28 target_dep      all     RegisterFile_Multi_Banked_05.ngc
    29 target_dep      RegisterFile_Multi_Banked_05.ngc        RegisterFile_Multi_Banked_05.prj
    30 target_dep      RegisterFile_Multi_Banked_05.prj        RegisterFile_Multi_Banked_05_bank_Pack.vhdl RegisterFile_Multi_Banked_05_bank.vhdl RegisterFile_Multi_Banked_05_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports.vhdl RegisterFile_Multi_Banked_05.vhdl
    31 
    32 # RegisterFile_Multi_Banked_06
    33 target_dep      all     RegisterFile_Multi_Banked_06.ngc
    34 target_dep      RegisterFile_Multi_Banked_06.ngc        RegisterFile_Multi_Banked_06.prj
    35 target_dep      RegisterFile_Multi_Banked_06.prj        RegisterFile_Multi_Banked_06_bank_Pack.vhdl RegisterFile_Multi_Banked_06_bank.vhdl RegisterFile_Multi_Banked_06_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports.vhdl RegisterFile_Multi_Banked_06.vhdl
    36 
    37 # RegisterFile_Multi_Banked_07
    38 target_dep      all     RegisterFile_Multi_Banked_07.ngc
    39 target_dep      RegisterFile_Multi_Banked_07.ngc        RegisterFile_Multi_Banked_07.prj
    40 target_dep      RegisterFile_Multi_Banked_07.prj        RegisterFile_Multi_Banked_07_bank_Pack.vhdl RegisterFile_Multi_Banked_07_bank.vhdl RegisterFile_Multi_Banked_07_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports.vhdl RegisterFile_Multi_Banked_07_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports.vhdl RegisterFile_Multi_Banked_07.vhdl
    41 
    42 # RegisterFile_Multi_Banked_08
    43 target_dep      all     RegisterFile_Multi_Banked_08.ngc
    44 target_dep      RegisterFile_Multi_Banked_08.ngc        RegisterFile_Multi_Banked_08.prj
    45 target_dep      RegisterFile_Multi_Banked_08.prj        RegisterFile_Multi_Banked_08_bank_Pack.vhdl RegisterFile_Multi_Banked_08_bank.vhdl RegisterFile_Multi_Banked_08_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports.vhdl RegisterFile_Multi_Banked_08_select_22_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_22_ports.vhdl RegisterFile_Multi_Banked_08.vhdl
    46 
    47 # RegisterFile_Multi_Banked_09
    48 target_dep      all     RegisterFile_Multi_Banked_09.ngc
    49 target_dep      RegisterFile_Multi_Banked_09.ngc        RegisterFile_Multi_Banked_09.prj
    50 target_dep      RegisterFile_Multi_Banked_09.prj        RegisterFile_Multi_Banked_09_bank_Pack.vhdl RegisterFile_Multi_Banked_09_bank.vhdl RegisterFile_Multi_Banked_09_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports.vhdl RegisterFile_Multi_Banked_09_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_3_ports.vhdl RegisterFile_Multi_Banked_09_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_4_ports.vhdl RegisterFile_Multi_Banked_09.vhdl
    51 
    52 # RegisterFile_Multi_Banked_10
    53 target_dep      all     RegisterFile_Multi_Banked_10.ngc
    54 target_dep      RegisterFile_Multi_Banked_10.ngc        RegisterFile_Multi_Banked_10.prj
    55 target_dep      RegisterFile_Multi_Banked_10.prj        RegisterFile_Multi_Banked_10_bank_Pack.vhdl RegisterFile_Multi_Banked_10_bank.vhdl RegisterFile_Multi_Banked_10_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports.vhdl RegisterFile_Multi_Banked_10.vhdl
    56 
    57 # RegisterFile_Multi_Banked_11
    58 target_dep      all     RegisterFile_Multi_Banked_11.ngc
    59 target_dep      RegisterFile_Multi_Banked_11.ngc        RegisterFile_Multi_Banked_11.prj
    60 target_dep      RegisterFile_Multi_Banked_11.prj        RegisterFile_Multi_Banked_11_bank_Pack.vhdl RegisterFile_Multi_Banked_11_bank.vhdl RegisterFile_Multi_Banked_11_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports.vhdl RegisterFile_Multi_Banked_11_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_2_ports.vhdl RegisterFile_Multi_Banked_11.vhdl
    61 
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