Ignore:
Timestamp:
Oct 13, 2010, 8:15:51 PM (14 years ago)
Author:
rosiere
Message:

1) add test with SPECINT2K
2) new config of Selftest
3) modif RAT to support multiple depth_save ... but not finish (need fix Update Prediction Table)
4) add Function_pointer but need fix

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest
Files:
4 edited
16 moved

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile

    r88 r145  
    99#-----[ Directory ]----------------------------------------
    1010DIR_COMPONENT                   = ../
    11 include                         $(DIR_COMPONENT)/Makefile.defs
     11include                         $(DIR_COMPONENT)/Makefile.defs                                                                                                                                                   
    1212
    1313LIBRARY                         = $(RegisterFile_Multi_Banked_LIBRARY)

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info

    r139 r145  
    11
    2 # RegisterFile_Multi_Banked_0
    3 target_dep      all     RegisterFile_Multi_Banked_0.ngc
    4 target_dep      RegisterFile_Multi_Banked_0.ngc RegisterFile_Multi_Banked_0.prj
    5 target_dep      RegisterFile_Multi_Banked_0.prj RegisterFile_Multi_Banked_0_bank_Pack.vhdl RegisterFile_Multi_Banked_0_bank.vhdl RegisterFile_Multi_Banked_0_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports.vhdl RegisterFile_Multi_Banked_0_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_2_ports.vhdl RegisterFile_Multi_Banked_0.vhdl
     2# info_00
     3target_dep      all     info_00.ngc
     4target_dep      info_00.ngc     info_00.prj
     5target_dep      info_00.prj     info_00_bank_Pack.vhdl info_00_bank.vhdl info_00_Pack.vhdl info_00_select_4_ports_Pack.vhdl info_00_select_4_ports.vhdl info_00_select_8_ports_Pack.vhdl info_00_select_8_ports.vhdl info_00.vhdl
    66
    7 # RegisterFile_Multi_Banked_1
    8 target_dep      all     RegisterFile_Multi_Banked_1.ngc
    9 target_dep      RegisterFile_Multi_Banked_1.ngc RegisterFile_Multi_Banked_1.prj
    10 target_dep      RegisterFile_Multi_Banked_1.prj RegisterFile_Multi_Banked_1_bank_Pack.vhdl RegisterFile_Multi_Banked_1_bank.vhdl RegisterFile_Multi_Banked_1_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports.vhdl RegisterFile_Multi_Banked_1_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_2_ports.vhdl RegisterFile_Multi_Banked_1.vhdl
     7# info_01
     8target_dep      all     info_01.ngc
     9target_dep      info_01.ngc     info_01.prj
     10target_dep      info_01.prj     info_01_bank_Pack.vhdl info_01_bank.vhdl info_01_Pack.vhdl info_01_select_4_ports_Pack.vhdl info_01_select_4_ports.vhdl info_01_select_8_ports_Pack.vhdl info_01_select_8_ports.vhdl info_01.vhdl
    1111
     12# info_02
     13target_dep      all     info_02.ngc
     14target_dep      info_02.ngc     info_02.prj
     15target_dep      info_02.prj     info_02_bank_Pack.vhdl info_02_bank.vhdl info_02_Pack.vhdl info_02_select_4_ports_Pack.vhdl info_02_select_4_ports.vhdl info_02_select_8_ports_Pack.vhdl info_02_select_8_ports.vhdl info_02.vhdl
     16
     17# info_03
     18target_dep      all     info_03.ngc
     19target_dep      info_03.ngc     info_03.prj
     20target_dep      info_03.prj     info_03_bank_Pack.vhdl info_03_bank.vhdl info_03_Pack.vhdl info_03_select_16_ports_Pack.vhdl info_03_select_16_ports.vhdl info_03_select_4_ports_Pack.vhdl info_03_select_4_ports.vhdl info_03.vhdl
     21
     22# info_04
     23target_dep      all     info_04.ngc
     24target_dep      info_04.ngc     info_04.prj
     25target_dep      info_04.prj     info_04_bank_Pack.vhdl info_04_bank.vhdl info_04_Pack.vhdl info_04_select_16_ports_Pack.vhdl info_04_select_16_ports.vhdl info_04_select_4_ports_Pack.vhdl info_04_select_4_ports.vhdl info_04.vhdl
     26
     27# info_05
     28target_dep      all     info_05.ngc
     29target_dep      info_05.ngc     info_05.prj
     30target_dep      info_05.prj     info_05_bank_Pack.vhdl info_05_bank.vhdl info_05_Pack.vhdl info_05_select_16_ports_Pack.vhdl info_05_select_16_ports.vhdl info_05_select_4_ports_Pack.vhdl info_05_select_4_ports.vhdl info_05.vhdl
     31
     32# result_06
     33target_dep      all     result_06.ngc
     34target_dep      result_06.ngc   result_06.prj
     35target_dep      result_06.prj   result_06_bank_Pack.vhdl result_06_bank.vhdl result_06_Pack.vhdl result_06_select_4_ports_Pack.vhdl result_06_select_4_ports.vhdl result_06_select_8_ports_Pack.vhdl result_06_select_8_ports.vhdl result_06.vhdl
     36
     37# result_07
     38target_dep      all     result_07.ngc
     39target_dep      result_07.ngc   result_07.prj
     40target_dep      result_07.prj   result_07_bank_Pack.vhdl result_07_bank.vhdl result_07_Pack.vhdl result_07_select_4_ports_Pack.vhdl result_07_select_4_ports.vhdl result_07_select_8_ports_Pack.vhdl result_07_select_8_ports.vhdl result_07.vhdl
     41
     42# result_08
     43target_dep      all     result_08.ngc
     44target_dep      result_08.ngc   result_08.prj
     45target_dep      result_08.prj   result_08_bank_Pack.vhdl result_08_bank.vhdl result_08_Pack.vhdl result_08_select_4_ports_Pack.vhdl result_08_select_4_ports.vhdl result_08_select_8_ports_Pack.vhdl result_08_select_8_ports.vhdl result_08.vhdl
     46
     47# result_09
     48target_dep      all     result_09.ngc
     49target_dep      result_09.ngc   result_09.prj
     50target_dep      result_09.prj   result_09_bank_Pack.vhdl result_09_bank.vhdl result_09_Pack.vhdl result_09_select_16_ports_Pack.vhdl result_09_select_16_ports.vhdl result_09_select_4_ports_Pack.vhdl result_09_select_4_ports.vhdl result_09.vhdl
     51
     52# result_10
     53target_dep      all     result_10.ngc
     54target_dep      result_10.ngc   result_10.prj
     55target_dep      result_10.prj   result_10_bank_Pack.vhdl result_10_bank.vhdl result_10_Pack.vhdl result_10_select_16_ports_Pack.vhdl result_10_select_16_ports.vhdl result_10_select_4_ports_Pack.vhdl result_10_select_4_ports.vhdl result_10.vhdl
     56
     57# result_11
     58target_dep      all     result_11.ngc
     59target_dep      result_11.ngc   result_11.prj
     60target_dep      result_11.prj   result_11_bank_Pack.vhdl result_11_bank.vhdl result_11_Pack.vhdl result_11_select_16_ports_Pack.vhdl result_11_select_16_ports.vhdl result_11_select_4_ports_Pack.vhdl result_11_select_4_ports.vhdl result_11.vhdl
     61

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/main.cpp

    r81 r145  
    88#include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/include/test.h"
    99
    10 #define NB_PARAMS 0
     10#define NB_PARAMS 8
    1111
    1212void usage (int argc, char * argv[])
    … …  
    4040    usage (argc, argv);
    4141
    42   const string   name      = argv[1];
     42  const string      name                  = argv[1];
    4343  const uint32_t    nb_port_read          = atoi(argv[2]);
    4444  const uint32_t    nb_port_write         = atoi(argv[3]);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp

    r131 r145  
    4242     _param,
    4343     _usage);
    44  
    45 #ifdef SYSTEMC
     44
     45#if 0 
     46// #ifdef SYSTEMC
     47
    4648  /*********************************************************************
    4749   * Déclarations des signaux
    … …  
    229231   ********************************************************/
    230232
    231   TEST_OK("End of Simulation");
    232233  delete _time;
    233234  cout << "<" << name << "> ............ Stop Simulation" << endl;
    … …  
    236237  delete NRESET;
    237238#endif
     239  TEST_OK("End of Simulation");
    238240
    239241  delete _RegisterFile_Multi_Banked;
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