Changeset 145 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info

Timestamp:

Oct 13, 2010, 8:15:51 PM (14 years ago)

Author:

rosiere

Message:

1) add test with SPECINT2K
2) new config of Selftest
3) modif RAT to support multiple depth_save ... but not finish (need fix Update Prediction Table)
4) add Function_pointer but need fix

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info (modified) (1 diff)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info

@@ -1 +1 @@
 
-# RegisterFile_Multi_Banked_0
-target_dep      all     RegisterFile_Multi_Banked_0.ngc
-target_dep      RegisterFile_Multi_Banked_0.ngc RegisterFile_Multi_Banked_0.prj
-target_dep      RegisterFile_Multi_Banked_0.prj RegisterFile_Multi_Banked_0_bank_Pack.vhdl RegisterFile_Multi_Banked_0_bank.vhdl RegisterFile_Multi_Banked_0_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_1_ports.vhdl RegisterFile_Multi_Banked_0_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_2_ports.vhdl RegisterFile_Multi_Banked_0.vhdl
+# info_00
+target_dep      all     info_00.ngc
+target_dep      info_00.ngc     info_00.prj
+target_dep      info_00.prj     info_00_bank_Pack.vhdl info_00_bank.vhdl info_00_Pack.vhdl info_00_select_4_ports_Pack.vhdl info_00_select_4_ports.vhdl info_00_select_8_ports_Pack.vhdl info_00_select_8_ports.vhdl info_00.vhdl
 
-# RegisterFile_Multi_Banked_1
-target_dep      all     RegisterFile_Multi_Banked_1.ngc
-target_dep      RegisterFile_Multi_Banked_1.ngc RegisterFile_Multi_Banked_1.prj
-target_dep      RegisterFile_Multi_Banked_1.prj RegisterFile_Multi_Banked_1_bank_Pack.vhdl RegisterFile_Multi_Banked_1_bank.vhdl RegisterFile_Multi_Banked_1_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_1_ports.vhdl RegisterFile_Multi_Banked_1_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_2_ports.vhdl RegisterFile_Multi_Banked_1.vhdl
+# info_01
+target_dep      all     info_01.ngc
+target_dep      info_01.ngc     info_01.prj
+target_dep      info_01.prj     info_01_bank_Pack.vhdl info_01_bank.vhdl info_01_Pack.vhdl info_01_select_4_ports_Pack.vhdl info_01_select_4_ports.vhdl info_01_select_8_ports_Pack.vhdl info_01_select_8_ports.vhdl info_01.vhdl
 
+# info_02
+target_dep      all     info_02.ngc
+target_dep      info_02.ngc     info_02.prj
+target_dep      info_02.prj     info_02_bank_Pack.vhdl info_02_bank.vhdl info_02_Pack.vhdl info_02_select_4_ports_Pack.vhdl info_02_select_4_ports.vhdl info_02_select_8_ports_Pack.vhdl info_02_select_8_ports.vhdl info_02.vhdl
+
+# info_03
+target_dep      all     info_03.ngc
+target_dep      info_03.ngc     info_03.prj
+target_dep      info_03.prj     info_03_bank_Pack.vhdl info_03_bank.vhdl info_03_Pack.vhdl info_03_select_16_ports_Pack.vhdl info_03_select_16_ports.vhdl info_03_select_4_ports_Pack.vhdl info_03_select_4_ports.vhdl info_03.vhdl
+
+# info_04
+target_dep      all     info_04.ngc
+target_dep      info_04.ngc     info_04.prj
+target_dep      info_04.prj     info_04_bank_Pack.vhdl info_04_bank.vhdl info_04_Pack.vhdl info_04_select_16_ports_Pack.vhdl info_04_select_16_ports.vhdl info_04_select_4_ports_Pack.vhdl info_04_select_4_ports.vhdl info_04.vhdl
+
+# info_05
+target_dep      all     info_05.ngc
+target_dep      info_05.ngc     info_05.prj
+target_dep      info_05.prj     info_05_bank_Pack.vhdl info_05_bank.vhdl info_05_Pack.vhdl info_05_select_16_ports_Pack.vhdl info_05_select_16_ports.vhdl info_05_select_4_ports_Pack.vhdl info_05_select_4_ports.vhdl info_05.vhdl
+
+# result_06
+target_dep      all     result_06.ngc
+target_dep      result_06.ngc   result_06.prj
+target_dep      result_06.prj   result_06_bank_Pack.vhdl result_06_bank.vhdl result_06_Pack.vhdl result_06_select_4_ports_Pack.vhdl result_06_select_4_ports.vhdl result_06_select_8_ports_Pack.vhdl result_06_select_8_ports.vhdl result_06.vhdl
+
+# result_07
+target_dep      all     result_07.ngc
+target_dep      result_07.ngc   result_07.prj
+target_dep      result_07.prj   result_07_bank_Pack.vhdl result_07_bank.vhdl result_07_Pack.vhdl result_07_select_4_ports_Pack.vhdl result_07_select_4_ports.vhdl result_07_select_8_ports_Pack.vhdl result_07_select_8_ports.vhdl result_07.vhdl
+
+# result_08
+target_dep      all     result_08.ngc
+target_dep      result_08.ngc   result_08.prj
+target_dep      result_08.prj   result_08_bank_Pack.vhdl result_08_bank.vhdl result_08_Pack.vhdl result_08_select_4_ports_Pack.vhdl result_08_select_4_ports.vhdl result_08_select_8_ports_Pack.vhdl result_08_select_8_ports.vhdl result_08.vhdl
+
+# result_09
+target_dep      all     result_09.ngc
+target_dep      result_09.ngc   result_09.prj
+target_dep      result_09.prj   result_09_bank_Pack.vhdl result_09_bank.vhdl result_09_Pack.vhdl result_09_select_16_ports_Pack.vhdl result_09_select_16_ports.vhdl result_09_select_4_ports_Pack.vhdl result_09_select_4_ports.vhdl result_09.vhdl
+
+# result_10
+target_dep      all     result_10.ngc
+target_dep      result_10.ngc   result_10.prj
+target_dep      result_10.prj   result_10_bank_Pack.vhdl result_10_bank.vhdl result_10_Pack.vhdl result_10_select_16_ports_Pack.vhdl result_10_select_16_ports.vhdl result_10_select_4_ports_Pack.vhdl result_10_select_4_ports.vhdl result_10.vhdl
+
+# result_11
+target_dep      all     result_11.ngc
+target_dep      result_11.ngc   result_11.prj
+target_dep      result_11.prj   result_11_bank_Pack.vhdl result_11_bank.vhdl result_11_Pack.vhdl result_11_select_16_ports_Pack.vhdl result_11_select_16_ports.vhdl result_11_select_4_ports_Pack.vhdl result_11_select_4_ports.vhdl result_11.vhdl
+