Ignore:
Timestamp:
May 21, 2007, 12:01:51 PM (17 years ago)
Author:
rosiere
Message:

Documentation pour chaque composant.
Documentation : ajout d'un poster et d'un article.
RegisterFile_Multi_Banked_Glue - non encore stable.

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile
Files:
51 added
15 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/Makefile

    r15 r23  
    88
    99#-----[ Directory ]----------------------------------------
    10 DIR_MORPHEO                     = ../../../..
     10DIR_COMPONENT                   = .
     11include                         $(DIR_COMPONENT)/Makefile.defs
    1112
    1213#-----[ Library ]------------------------------------------
    … …  
    1920                                @$(MAKE) all_component
    2021
    21 include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
     22include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
    2223include                         $(DIR_MORPHEO)/Behavioural/Makefile.Common
    2324include                         $(DIR_MORPHEO)/Behavioural/Makefile.Component

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/Makefile

    r15 r23  
    2424
    2525include                         ../Makefile.deps
    26 include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
     26include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
    2727include                         $(DIR_MORPHEO)/Behavioural/Makefile.Common
    2828include                         $(DIR_MORPHEO)/Behavioural/Makefile.Selftest

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/configuration.cfg

    r15 r23  
    11RegisterFile_Monolithic
    2 1       8       *2      # nb_port_read
     22       8       *2      # nb_port_read
    331       4       *2      # nb_port_write
    4 64      256     *2      # nb_word
     432      256     *2      # nb_word
    5532      32      *2      # size_word

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info

    r6 r23  
    11
    2 # RegisterFile_34
    3 target_dep      all     RegisterFile_34.ngc
    4 target_dep      RegisterFile_34.ngc     RegisterFile_34.prj
    5 target_dep      RegisterFile_34.prj     RegisterFile_34_Pack.vhdl RegisterFile_34.vhdl
     2# RegisterFile_Monolithic_0
     3target_dep      all     RegisterFile_Monolithic_0.ngc
     4target_dep      RegisterFile_Monolithic_0.ngc   RegisterFile_Monolithic_0.prj
     5target_dep      RegisterFile_Monolithic_0.prj   RegisterFile_Monolithic_0_Pack.vhdl RegisterFile_Monolithic_0.vhdl
    66
    7 # RegisterFile_35
    8 target_dep      all     RegisterFile_35.ngc
    9 target_dep      RegisterFile_35.ngc     RegisterFile_35.prj
    10 target_dep      RegisterFile_35.prj     RegisterFile_35_Pack.vhdl RegisterFile_35.vhdl
     7# RegisterFile_Monolithic_10
     8target_dep      all     RegisterFile_Monolithic_10.ngc
     9target_dep      RegisterFile_Monolithic_10.ngc  RegisterFile_Monolithic_10.prj
     10target_dep      RegisterFile_Monolithic_10.prj  RegisterFile_Monolithic_10_Pack.vhdl RegisterFile_Monolithic_10.vhdl
    1111
     12# RegisterFile_Monolithic_11
     13target_dep      all     RegisterFile_Monolithic_11.ngc
     14target_dep      RegisterFile_Monolithic_11.ngc  RegisterFile_Monolithic_11.prj
     15target_dep      RegisterFile_Monolithic_11.prj  RegisterFile_Monolithic_11_Pack.vhdl RegisterFile_Monolithic_11.vhdl
     16
     17# RegisterFile_Monolithic_12
     18target_dep      all     RegisterFile_Monolithic_12.ngc
     19target_dep      RegisterFile_Monolithic_12.ngc  RegisterFile_Monolithic_12.prj
     20target_dep      RegisterFile_Monolithic_12.prj  RegisterFile_Monolithic_12_Pack.vhdl RegisterFile_Monolithic_12.vhdl
     21
     22# RegisterFile_Monolithic_13
     23target_dep      all     RegisterFile_Monolithic_13.ngc
     24target_dep      RegisterFile_Monolithic_13.ngc  RegisterFile_Monolithic_13.prj
     25target_dep      RegisterFile_Monolithic_13.prj  RegisterFile_Monolithic_13_Pack.vhdl RegisterFile_Monolithic_13.vhdl
     26
     27# RegisterFile_Monolithic_14
     28target_dep      all     RegisterFile_Monolithic_14.ngc
     29target_dep      RegisterFile_Monolithic_14.ngc  RegisterFile_Monolithic_14.prj
     30target_dep      RegisterFile_Monolithic_14.prj  RegisterFile_Monolithic_14_Pack.vhdl RegisterFile_Monolithic_14.vhdl
     31
     32# RegisterFile_Monolithic_15
     33target_dep      all     RegisterFile_Monolithic_15.ngc
     34target_dep      RegisterFile_Monolithic_15.ngc  RegisterFile_Monolithic_15.prj
     35target_dep      RegisterFile_Monolithic_15.prj  RegisterFile_Monolithic_15_Pack.vhdl RegisterFile_Monolithic_15.vhdl
     36
     37# RegisterFile_Monolithic_16
     38target_dep      all     RegisterFile_Monolithic_16.ngc
     39target_dep      RegisterFile_Monolithic_16.ngc  RegisterFile_Monolithic_16.prj
     40target_dep      RegisterFile_Monolithic_16.prj  RegisterFile_Monolithic_16_Pack.vhdl RegisterFile_Monolithic_16.vhdl
     41
     42# RegisterFile_Monolithic_17
     43target_dep      all     RegisterFile_Monolithic_17.ngc
     44target_dep      RegisterFile_Monolithic_17.ngc  RegisterFile_Monolithic_17.prj
     45target_dep      RegisterFile_Monolithic_17.prj  RegisterFile_Monolithic_17_Pack.vhdl RegisterFile_Monolithic_17.vhdl
     46
     47# RegisterFile_Monolithic_18
     48target_dep      all     RegisterFile_Monolithic_18.ngc
     49target_dep      RegisterFile_Monolithic_18.ngc  RegisterFile_Monolithic_18.prj
     50target_dep      RegisterFile_Monolithic_18.prj  RegisterFile_Monolithic_18_Pack.vhdl RegisterFile_Monolithic_18.vhdl
     51
     52# RegisterFile_Monolithic_19
     53target_dep      all     RegisterFile_Monolithic_19.ngc
     54target_dep      RegisterFile_Monolithic_19.ngc  RegisterFile_Monolithic_19.prj
     55target_dep      RegisterFile_Monolithic_19.prj  RegisterFile_Monolithic_19_Pack.vhdl RegisterFile_Monolithic_19.vhdl
     56
     57# RegisterFile_Monolithic_1
     58target_dep      all     RegisterFile_Monolithic_1.ngc
     59target_dep      RegisterFile_Monolithic_1.ngc   RegisterFile_Monolithic_1.prj
     60target_dep      RegisterFile_Monolithic_1.prj   RegisterFile_Monolithic_10_Pack.vhdl RegisterFile_Monolithic_10.vhdl RegisterFile_Monolithic_11_Pack.vhdl RegisterFile_Monolithic_11.vhdl RegisterFile_Monolithic_12_Pack.vhdl RegisterFile_Monolithic_12.vhdl RegisterFile_Monolithic_13_Pack.vhdl RegisterFile_Monolithic_13.vhdl RegisterFile_Monolithic_14_Pack.vhdl RegisterFile_Monolithic_14.vhdl RegisterFile_Monolithic_15_Pack.vhdl RegisterFile_Monolithic_15.vhdl RegisterFile_Monolithic_16_Pack.vhdl RegisterFile_Monolithic_16.vhdl RegisterFile_Monolithic_17_Pack.vhdl RegisterFile_Monolithic_17.vhdl RegisterFile_Monolithic_18_Pack.vhdl RegisterFile_Monolithic_18.vhdl RegisterFile_Monolithic_19_Pack.vhdl RegisterFile_Monolithic_19.vhdl RegisterFile_Monolithic_1_Pack.vhdl RegisterFile_Monolithic_1.vhdl
     61
     62# RegisterFile_Monolithic_20
     63target_dep      all     RegisterFile_Monolithic_20.ngc
     64target_dep      RegisterFile_Monolithic_20.ngc  RegisterFile_Monolithic_20.prj
     65target_dep      RegisterFile_Monolithic_20.prj  RegisterFile_Monolithic_20_Pack.vhdl RegisterFile_Monolithic_20.vhdl
     66
     67# RegisterFile_Monolithic_21
     68target_dep      all     RegisterFile_Monolithic_21.ngc
     69target_dep      RegisterFile_Monolithic_21.ngc  RegisterFile_Monolithic_21.prj
     70target_dep      RegisterFile_Monolithic_21.prj  RegisterFile_Monolithic_21_Pack.vhdl RegisterFile_Monolithic_21.vhdl
     71
     72# RegisterFile_Monolithic_22
     73target_dep      all     RegisterFile_Monolithic_22.ngc
     74target_dep      RegisterFile_Monolithic_22.ngc  RegisterFile_Monolithic_22.prj
     75target_dep      RegisterFile_Monolithic_22.prj  RegisterFile_Monolithic_22_Pack.vhdl RegisterFile_Monolithic_22.vhdl
     76
     77# RegisterFile_Monolithic_23
     78target_dep      all     RegisterFile_Monolithic_23.ngc
     79target_dep      RegisterFile_Monolithic_23.ngc  RegisterFile_Monolithic_23.prj
     80target_dep      RegisterFile_Monolithic_23.prj  RegisterFile_Monolithic_23_Pack.vhdl RegisterFile_Monolithic_23.vhdl
     81
     82# RegisterFile_Monolithic_24
     83target_dep      all     RegisterFile_Monolithic_24.ngc
     84target_dep      RegisterFile_Monolithic_24.ngc  RegisterFile_Monolithic_24.prj
     85target_dep      RegisterFile_Monolithic_24.prj  RegisterFile_Monolithic_24_Pack.vhdl RegisterFile_Monolithic_24.vhdl
     86
     87# RegisterFile_Monolithic_25
     88target_dep      all     RegisterFile_Monolithic_25.ngc
     89target_dep      RegisterFile_Monolithic_25.ngc  RegisterFile_Monolithic_25.prj
     90target_dep      RegisterFile_Monolithic_25.prj  RegisterFile_Monolithic_25_Pack.vhdl RegisterFile_Monolithic_25.vhdl
     91
     92# RegisterFile_Monolithic_26
     93target_dep      all     RegisterFile_Monolithic_26.ngc
     94target_dep      RegisterFile_Monolithic_26.ngc  RegisterFile_Monolithic_26.prj
     95target_dep      RegisterFile_Monolithic_26.prj  RegisterFile_Monolithic_26_Pack.vhdl RegisterFile_Monolithic_26.vhdl
     96
     97# RegisterFile_Monolithic_27
     98target_dep      all     RegisterFile_Monolithic_27.ngc
     99target_dep      RegisterFile_Monolithic_27.ngc  RegisterFile_Monolithic_27.prj
     100target_dep      RegisterFile_Monolithic_27.prj  RegisterFile_Monolithic_27_Pack.vhdl RegisterFile_Monolithic_27.vhdl
     101
     102# RegisterFile_Monolithic_28
     103target_dep      all     RegisterFile_Monolithic_28.ngc
     104target_dep      RegisterFile_Monolithic_28.ngc  RegisterFile_Monolithic_28.prj
     105target_dep      RegisterFile_Monolithic_28.prj  RegisterFile_Monolithic_28_Pack.vhdl RegisterFile_Monolithic_28.vhdl
     106
     107# RegisterFile_Monolithic_29
     108target_dep      all     RegisterFile_Monolithic_29.ngc
     109target_dep      RegisterFile_Monolithic_29.ngc  RegisterFile_Monolithic_29.prj
     110target_dep      RegisterFile_Monolithic_29.prj  RegisterFile_Monolithic_29_Pack.vhdl RegisterFile_Monolithic_29.vhdl
     111
     112# RegisterFile_Monolithic_2
     113target_dep      all     RegisterFile_Monolithic_2.ngc
     114target_dep      RegisterFile_Monolithic_2.ngc   RegisterFile_Monolithic_2.prj
     115target_dep      RegisterFile_Monolithic_2.prj   RegisterFile_Monolithic_20_Pack.vhdl RegisterFile_Monolithic_20.vhdl RegisterFile_Monolithic_21_Pack.vhdl RegisterFile_Monolithic_21.vhdl RegisterFile_Monolithic_22_Pack.vhdl RegisterFile_Monolithic_22.vhdl RegisterFile_Monolithic_23_Pack.vhdl RegisterFile_Monolithic_23.vhdl RegisterFile_Monolithic_24_Pack.vhdl RegisterFile_Monolithic_24.vhdl RegisterFile_Monolithic_25_Pack.vhdl RegisterFile_Monolithic_25.vhdl RegisterFile_Monolithic_26_Pack.vhdl RegisterFile_Monolithic_26.vhdl RegisterFile_Monolithic_27_Pack.vhdl RegisterFile_Monolithic_27.vhdl RegisterFile_Monolithic_28_Pack.vhdl RegisterFile_Monolithic_28.vhdl RegisterFile_Monolithic_29_Pack.vhdl RegisterFile_Monolithic_29.vhdl RegisterFile_Monolithic_2_Pack.vhdl RegisterFile_Monolithic_2.vhdl
     116
     117# RegisterFile_Monolithic_30
     118target_dep      all     RegisterFile_Monolithic_30.ngc
     119target_dep      RegisterFile_Monolithic_30.ngc  RegisterFile_Monolithic_30.prj
     120target_dep      RegisterFile_Monolithic_30.prj  RegisterFile_Monolithic_30_Pack.vhdl RegisterFile_Monolithic_30.vhdl
     121
     122# RegisterFile_Monolithic_31
     123target_dep      all     RegisterFile_Monolithic_31.ngc
     124target_dep      RegisterFile_Monolithic_31.ngc  RegisterFile_Monolithic_31.prj
     125target_dep      RegisterFile_Monolithic_31.prj  RegisterFile_Monolithic_31_Pack.vhdl RegisterFile_Monolithic_31.vhdl
     126
     127# RegisterFile_Monolithic_32
     128target_dep      all     RegisterFile_Monolithic_32.ngc
     129target_dep      RegisterFile_Monolithic_32.ngc  RegisterFile_Monolithic_32.prj
     130target_dep      RegisterFile_Monolithic_32.prj  RegisterFile_Monolithic_32_Pack.vhdl RegisterFile_Monolithic_32.vhdl
     131
     132# RegisterFile_Monolithic_33
     133target_dep      all     RegisterFile_Monolithic_33.ngc
     134target_dep      RegisterFile_Monolithic_33.ngc  RegisterFile_Monolithic_33.prj
     135target_dep      RegisterFile_Monolithic_33.prj  RegisterFile_Monolithic_33_Pack.vhdl RegisterFile_Monolithic_33.vhdl
     136
     137# RegisterFile_Monolithic_34
     138target_dep      all     RegisterFile_Monolithic_34.ngc
     139target_dep      RegisterFile_Monolithic_34.ngc  RegisterFile_Monolithic_34.prj
     140target_dep      RegisterFile_Monolithic_34.prj  RegisterFile_Monolithic_34_Pack.vhdl RegisterFile_Monolithic_34.vhdl
     141
     142# RegisterFile_Monolithic_35
     143target_dep      all     RegisterFile_Monolithic_35.ngc
     144target_dep      RegisterFile_Monolithic_35.ngc  RegisterFile_Monolithic_35.prj
     145target_dep      RegisterFile_Monolithic_35.prj  RegisterFile_Monolithic_35_Pack.vhdl RegisterFile_Monolithic_35.vhdl
     146
     147# RegisterFile_Monolithic_3
     148target_dep      all     RegisterFile_Monolithic_3.ngc
     149target_dep      RegisterFile_Monolithic_3.ngc   RegisterFile_Monolithic_3.prj
     150target_dep      RegisterFile_Monolithic_3.prj   RegisterFile_Monolithic_30_Pack.vhdl RegisterFile_Monolithic_30.vhdl RegisterFile_Monolithic_31_Pack.vhdl RegisterFile_Monolithic_31.vhdl RegisterFile_Monolithic_32_Pack.vhdl RegisterFile_Monolithic_32.vhdl RegisterFile_Monolithic_33_Pack.vhdl RegisterFile_Monolithic_33.vhdl RegisterFile_Monolithic_34_Pack.vhdl RegisterFile_Monolithic_34.vhdl RegisterFile_Monolithic_35_Pack.vhdl RegisterFile_Monolithic_35.vhdl RegisterFile_Monolithic_3_Pack.vhdl RegisterFile_Monolithic_3.vhdl
     151
     152# RegisterFile_Monolithic_4
     153target_dep      all     RegisterFile_Monolithic_4.ngc
     154target_dep      RegisterFile_Monolithic_4.ngc   RegisterFile_Monolithic_4.prj
     155target_dep      RegisterFile_Monolithic_4.prj   RegisterFile_Monolithic_4_Pack.vhdl RegisterFile_Monolithic_4.vhdl
     156
     157# RegisterFile_Monolithic_5
     158target_dep      all     RegisterFile_Monolithic_5.ngc
     159target_dep      RegisterFile_Monolithic_5.ngc   RegisterFile_Monolithic_5.prj
     160target_dep      RegisterFile_Monolithic_5.prj   RegisterFile_Monolithic_5_Pack.vhdl RegisterFile_Monolithic_5.vhdl
     161
     162# RegisterFile_Monolithic_6
     163target_dep      all     RegisterFile_Monolithic_6.ngc
     164target_dep      RegisterFile_Monolithic_6.ngc   RegisterFile_Monolithic_6.prj
     165target_dep      RegisterFile_Monolithic_6.prj   RegisterFile_Monolithic_6_Pack.vhdl RegisterFile_Monolithic_6.vhdl
     166
     167# RegisterFile_Monolithic_7
     168target_dep      all     RegisterFile_Monolithic_7.ngc
     169target_dep      RegisterFile_Monolithic_7.ngc   RegisterFile_Monolithic_7.prj
     170target_dep      RegisterFile_Monolithic_7.prj   RegisterFile_Monolithic_7_Pack.vhdl RegisterFile_Monolithic_7.vhdl
     171
     172# RegisterFile_Monolithic_8
     173target_dep      all     RegisterFile_Monolithic_8.ngc
     174target_dep      RegisterFile_Monolithic_8.ngc   RegisterFile_Monolithic_8.prj
     175target_dep      RegisterFile_Monolithic_8.prj   RegisterFile_Monolithic_8_Pack.vhdl RegisterFile_Monolithic_8.vhdl
     176
     177# RegisterFile_Monolithic_9
     178target_dep      all     RegisterFile_Monolithic_9.ngc
     179target_dep      RegisterFile_Monolithic_9.ngc   RegisterFile_Monolithic_9.prj
     180target_dep      RegisterFile_Monolithic_9.prj   RegisterFile_Monolithic_9_Pack.vhdl RegisterFile_Monolithic_9.vhdl
     181

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/Makefile

    r15 r23  
    88
    99#-----[ Directory ]----------------------------------------
    10 DIR_MORPHEO                     = ../../../..
     10DIR_COMPONENT                   = .
     11include                         $(DIR_COMPONENT)/Makefile.defs
    1112
    1213#-----[ Library ]------------------------------------------
    … …  
    1920                                @$(MAKE) all_component
    2021
    21 include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
     22include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
    2223include                         $(DIR_MORPHEO)/Behavioural/Makefile.Common
    2324include                         $(DIR_MORPHEO)/Behavioural/Makefile.Component

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/Makefile

    r15 r23  
    88
    99#-----[ Directory ]----------------------------------------
    10 DIR_MORPHEO                     = ../../../../..
     10DIR_COMPONENT                   = .
     11include                         $(DIR_COMPONENT)/Makefile.defs
    1112
    1213#-----[ Library ]------------------------------------------
    … …  
    1920                                @$(MAKE) all_component
    2021
    21 include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
     22include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
    2223include                         $(DIR_MORPHEO)/Behavioural/Makefile.Common
    2324include                         $(DIR_MORPHEO)/Behavioural/Makefile.Component

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/Makefile

    r15 r23  
    88
    99#-----[ Directory ]----------------------------------------
    10 DIR_MORPHEO                     = ../../../../../..
     10DIR_COMPONENT                   = ..
     11include                         $(DIR_COMPONENT)/Makefile.defs
    1112
    1213LIBRARY                         = $(RegisterFile_Multi_Banked_Glue_LIBRARY)
    … …  
    2324library_clean                   : RegisterFile_Multi_Banked_Glue_library_clean
    2425
    25 include                         ../Makefile.deps
    26 include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
     26include                         $(DIR_COMPONENT)/Makefile.deps
     27include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
    2728include                         $(DIR_MORPHEO)/Behavioural/Makefile.Common
    2829include                         $(DIR_MORPHEO)/Behavioural/Makefile.Selftest

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/configuration.cfg

    r15 r23  
    11RegisterFile_Multi_Banked_Glue
    2 4       4       *2      # nb_port_read
     211      11      *2      # nb_port_read
    334       4       *2      # nb_port_write
    448       8       +1      # size_address
    5532      32      *2      # size_word
    6 2       2       *2      # nb_bank
    7 2       2       *2      # nb_port_read_by_bank
     64       4       *2      # nb_bank
     73       3       *2      # nb_port_read_by_bank
    882       2       *2      # nb_port_write_by_bank
    9 0       1       +1      # crossbar
     90       0       +1      # crossbar

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp

    r15 r23  
    99#define NB_ITERATION 16
    1010
     11#define TEXT(str)  do {cout << "<" << name << "> : " << str << endl;} while (0)
    1112#define LABEL(str) do {cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; _RegisterFile_Multi_Banked_Glue->vhdl_testbench_label(str);} while (0)
    1213
    … …  
    1819           morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::Parameters _param)
    1920{
    20   cout << "<" << name << "> : Simulation SystemC" << endl;
     21  TEXT("Simulation SystemC");
    2122
    2223  RegisterFile_Multi_Banked_Glue * _RegisterFile_Multi_Banked_Glue = new RegisterFile_Multi_Banked_Glue (name.c_str(),
    … …  
    192193   ********************************************************/
    193194 
    194   cout << "<" << name << "> Instanciation of _RegisterFile_Multi_Banked_Glue" << endl;
     195   TEXT("Instanciation of _RegisterFile_Multi_Banked_Glue");
    195196 
    196197  (*(_RegisterFile_Multi_Banked_Glue->in_CLOCK))        (*(CLOCK));
    … …  
    247248
    248249
    249   cout << "<" << name << "> Start Simulation ............" << endl;
     250   TEXT("Start Simulation ............");
    250251 
    251252  /********************************************************
    … …  
    265266
    266267  uint32_t   read_in_num_bank [_param._nb_port_read]; // Number of bank
    267 //Tcontrol_t read_in_valid    [_param._nb_port_read];
     268  Tcontrol_t read_is_busy     [_param._nb_port_read];
     269  bool       read_out_find    [_param._nb_bank][_param._nb_port_read_by_bank]; 
     270  uint32_t   read_out_port    [_param._nb_bank][_param._nb_port_read_by_bank]; 
     271
    268272  Tcontrol_t read_in_ack      [_param._nb_port_read]; // to test
    269273  Tdata_t    read_in_data     [_param._nb_port_read]; // to test
    270274  Tcontrol_t read_out_val     [_param._nb_bank][_param._nb_port_read_by_bank]; 
    271   Tcontrol_t read_out_ack     [_param._nb_bank][_param._nb_port_read_by_bank]; 
    272275  Taddress_t read_out_address [_param._nb_bank][_param._nb_port_read_by_bank]; 
    273   Tcontrol_t read_is_busy     [_param._nb_port_read];
    274   Tcontrol_t read_select_val  [_param._nb_bank][_param._nb_port_read        ];
    275   Tcontrol_t read_select_ack  [_param._nb_bank][_param._nb_port_read        ];
     276  Tcontrol_t read_select_val  [_param._nb_bank][_param._nb_port_read_by_bank][_param._nb_port_read];
    276277
    277278  LABEL("Loop of Test");
    … …  
    281282      LABEL("Iteration "+toString(iteration));
    282283     
    283       LABEL("Test read_in");
     284      //LABEL("Test read_in");
    284285     
    285286      // Write in interface "read_in"
    … …  
    287288        {
    288289          read_in_num_bank  [i] =  rand() % _param._nb_bank;
    289           Tcontrol_t read_in_valid = (rand() % 2) != 0;
     290          Tcontrol_t read_in_val = (rand() % 2) != 0;
    290291
    291292          Taddress_t address    = (read_in_num_bank[i] << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i);
    292293
    293           read_is_busy      [i] = (read_in_valid == 0);
    294           read_in_ack       [i] = 0;
    295           read_in_data      [i] = 0;
    296           READ_IN_VAL       [i]->write(read_in_valid);
    297           READ_IN_ADDRESS   [i]->write(address);
    298 
    299           for (uint32_t j=0; j<_param._nb_bank; j++)
    300             read_select_ack [j][i] = 0;
     294          read_is_busy      [i] = (read_in_val == 0);   // invalid = busy
     295          read_in_ack       [i] = 0;                    // init
     296          read_in_data      [i] = 0;                    // init
     297          READ_IN_VAL       [i]->write(read_in_val);    // write signal
     298          READ_IN_ADDRESS   [i]->write(address);        // write signal
    301299        }
    302300
    303       for (uint32_t i=0; i<_param._nb_bank; i++)
    304         for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
    305           {
    306             read_out_ack      [i][j] = (rand() % 2) != 0;
    307             READ_OUT_ACK      [i][j]->write(read_out_ack      [i][j]);
    308             READ_OUT_DATA     [i][j]->write((j<<1)|1); // (j<<1)|1 afin de n'avoir jamais 0
    309           }
    310      
    311301      // compute the good read_select
    312302      for (uint32_t i=0; i<_param._nb_bank; i++)
    313303        for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
    314304          {
     305            Tcontrol_t read_out_ack = (rand() % 2) != 0;
     306            READ_OUT_ACK     [i][j]->write(read_out_ack);
     307            READ_OUT_DATA    [i][j]->write((j<<1)|1);            // (j<<1)|1 afin de n'avoir jamais 0
     308
     309            read_out_find    [i][j] = false;
     310            read_out_port    [i][j] = 0;
     311
     312            read_out_val     [i][j] = 0;
     313            read_out_address [i][j] = 0;
     314
    315315            bool find = false; // have find a port_in to link with this port_out
    316316            for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
    317317              {
    318 
    319318                uint32_t num_port; // number of port
    320319               
    … …  
    323322                  num_port = k;
    324323                else
    325                   num_port = _param._link_port_read [i];
    326 
    327                 read_select_val [i][num_port] = read_out_ack [i][j] && not read_is_busy [num_port];
    328                
    329                 if ((read_out_ack [i][j] == 0) || find)
    330                   read_select_ack [i][num_port] = 0; // read_out is busy or already find
    331                 else
     324                  num_port = k*_param._nb_port_read_by_bank+j;
     325
     326                read_select_val [i][j][k] = read_out_ack and not read_is_busy [num_port] and (read_in_num_bank[num_port] == i); // select val if port is not busy and out accept a data
     327                Tcontrol_t read_select_ack = 0;
     328
     329                // test a previous find
     330                if (not ((read_out_ack == 0) || find))
    332331                  {
    333332                    // find a busy port?
    334                     find = not read_is_busy [num_port];
    335                     read_is_busy       [num_port]|= find;
    336                     read_select_ack [i][num_port] = find;
     333                    find                      = read_select_val;
     334                    read_is_busy   [num_port]|= find; // port became busy if find
     335                    read_select_ack           = find; // ack if find
    337336
    338337                    if (find)
    339338                      {
     339                        read_out_find    [i][j] = true;
     340                        read_out_port    [i][j] = num_port;
     341
     342                        // know the good output
    340343                        read_in_ack      [num_port] = 1;
    341344                        read_in_data     [num_port] = ((j<<1)|1);
    342345                        read_out_val     [i][j]     = 1;
    343                         read_out_address [i][j]     = (read_in_num_bank[i] << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i);
     346                        read_out_address [i][j]     = (i << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & num_port);
    344347                      }
    345348                  }
    346349               
    347                 READ_SELECT_ACK [i][j][k]->write(read_select_ack [i][num_port]);
     350                READ_SELECT_ACK [i][j][k]->write(read_select_ack);
    348351              }
    349352          }
    … …  
    352355      sc_start(1);
    353356
    354 //       // lot of test
    355 //   public    : SC_OUT(Tcontrol_t)           ** out_READ_IN_ACK       ;
    356 //   public    : SC_OUT(Tdata_t   )           ** out_READ_IN_DATA      ;
    357 
    358 //   public    : SC_OUT(Tcontrol_t)         **** out_READ_SELECT_VAL   ;
    359 
    360 //   public    : SC_OUT(Tcontrol_t)          *** out_READ_OUT_VAL      ;
    361 //   public    : SC_OUT(Taddress_t)          *** out_READ_OUT_ADDRESS  ;
     357      // test output
     358
     359      TEXT ("===== Test Output =====");
     360      for (uint32_t i=0; i<_param._nb_port_read; i++)
     361        {
     362          TEXT ("Read_in         [" << i << "]       : "
     363                << READ_IN_VAL [i]->read() << ","
     364                << read_in_ack [i]         << " - "
     365                << "Reg[" << READ_IN_ADDRESS [i]->read() << "] -> "
     366                << read_in_data [i] << " "
     367                << "{bank : " << read_in_num_bank[i] << "}"
     368                );
     369
     370          TEST (Tcontrol_t, read_in_ack  [i], READ_IN_ACK  [i]->read());
     371          if (READ_IN_VAL [i]->read() and READ_IN_ACK [i]->read())
     372          TEST (Tdata_t   , read_in_data [i], READ_IN_DATA [i]->read());
     373        }
     374
     375      cout << endl;
     376      for (uint32_t i=0; i<_param._nb_bank; i++)
     377        for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
     378          {
     379            TEXT ("Read_out        [" << i << "][" << j << "]    : "
     380                  << read_out_val [i][j]         << ","
     381                  << READ_OUT_ACK [i][j]->read() << " - "
     382                  << "Reg[" << read_out_address [i][j] << "] -> "
     383                  << READ_OUT_DATA [i][j]->read() << " - "
     384                  << "[" << read_out_find [i][j]<< " , "
     385                  << read_out_port    [i][j] << "]"               
     386                  );
     387
     388            TEST (Tcontrol_t, read_out_val     [i][j], READ_OUT_VAL     [i][j]->read());
     389            if (READ_OUT_VAL [i][j]->read() and READ_OUT_ACK [i][j]->read())
     390            TEST (Taddress_t, read_out_address [i][j], READ_OUT_ADDRESS [i][j]->read());
     391
     392            for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
     393              {
     394                uint32_t num_port; // number of port
     395               
     396                // compute the good number of port
     397                if (_param._crossbar == FULL_CROSSBAR)
     398                  num_port = k;
     399                else
     400                  num_port = k*_param._nb_port_read_by_bank+j;
     401               
     402                TEXT (" * Read_select  [" << i << "][" << j << "][" << k << "] : "
     403                      << read_select_val [i][j][k]         << ","
     404                      << READ_SELECT_ACK [i][j][k]->read() << " - "
     405                      << "link with read_in[" << num_port << "]"
     406                      );
     407               
     408                TEST (Tcontrol_t, read_select_val  [i][j][k], READ_SELECT_VAL  [i][j][k]->read());
     409              }
     410           
     411           
     412           
     413          }
    362414
    363415    }
     416
     417  sc_start(0);
    364418
    365419  /********************************************************
    … …  
    367421   ********************************************************/
    368422
    369   cout << "<" << name << "> ............ Stop Simulation" << endl;
     423  TEXT("............ Stop Simulation");
    370424
    371425  delete CLOCK;
    372426
     427  TEXT("delete read_in");
    373428  for (uint32_t i=0; i<_param._nb_port_read; i++)
    374429    {
     430//       TEXT("1, i " << i);
    375431      delete READ_IN_VAL       [i];
     432//       TEXT("2");
    376433      delete READ_IN_ACK       [i];
     434//       TEXT("3");
    377435      delete READ_IN_ADDRESS   [i];
     436//       TEXT("4");
    378437      delete READ_IN_DATA      [i];
     438//       TEXT("5");
    379439    }
    380440                                                     
    … …  
    384444  delete READ_IN_DATA   ;
    385445
     446  TEXT("delete read_select");
    386447   for (uint32_t i=0; i<_param._nb_bank; i++)
    387448     {
    … …  
    402463   delete READ_SELECT_ACK;
    403464
     465  TEXT("delete read_out");
    404466   for (uint32_t i=0; i<_param._nb_bank; i++)
    405467     {
    … …  
    423485  delete READ_OUT_DATA   ;
    424486
     487  TEXT("delete write_in");
    425488  for (uint32_t i=0; i<_param._nb_port_write; i++)
    426489    {
    … …  
    436499  delete WRITE_IN_DATA   ;
    437500
     501  TEXT("delete write_select");
    438502  for (uint32_t i=0; i<_param._nb_bank; i++)
    439503    {
    … …  
    454518  delete WRITE_SELECT_ACK;
    455519 
     520  TEXT("delete write_out");
    456521  for (uint32_t i=0; i<_param._nb_bank; i++)
    457522    {
    … …  
    477542#endif
    478543
     544
    479545  delete _RegisterFile_Multi_Banked_Glue;
    480546}

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/include/Parameters.h

    r15 r23  
    6363  public : const uint32_t    _shift_address        ;
    6464
    65   public :       uint32_t  * _link_port_read       ;
    66   public :       uint32_t  * _link_port_write      ;
    67 
    68   public :       uint32_t  * _nb_port_select_by_bank_read_port ;
    69   public :       uint32_t  * _nb_port_select_by_bank_write_port;
     65    // A lot of table to the partial crossbar
     66  public :       uint32_t  * _link_port_read_in_to_out    ;
     67  public :       uint32_t  * _link_port_read_in_to_select ;
     68  public :       uint32_t  * _link_port_write_in_to_out  ;
     69  public :       uint32_t  * _link_port_write_in_to_select;
    7070
    7171    //-----[ methods ]-----------------------------------------------------------
    … …  
    8282  public : ~Parameters () ;
    8383
    84   public : string msg_error (void);
     84  public : string msg_error           (void);
    8585
    8686  public :        string   print      (uint32_t depth);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/include/RegisterFile_Multi_Banked_Glue.h

    r15 r23  
    119119                                               
    120120#ifdef SYSTEMC                                 
     121    // function pointer
     122  public : uint32_t  (morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::*link_port_read_in_to_out    ) (uint32_t, uint32_t);
     123  public : uint32_t  (morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::*link_port_read_in_to_select ) (uint32_t, uint32_t);
     124  public : uint32_t  (morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::*link_port_write_in_to_out   ) (uint32_t, uint32_t);
     125  public : uint32_t  (morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::*link_port_write_in_to_select) (uint32_t, uint32_t);
     126
     127  public : uint32_t  full_crossbar_link_port_read_in_to_out        (uint32_t num_port, uint32_t num_bank);
     128  public : uint32_t  full_crossbar_link_port_read_in_to_select     (uint32_t num_port, uint32_t num_bank);
     129  public : uint32_t  full_crossbar_link_port_write_in_to_out       (uint32_t num_port, uint32_t num_bank);
     130  public : uint32_t  full_crossbar_link_port_write_in_to_select    (uint32_t num_port, uint32_t num_bank);
     131  public : uint32_t  partial_crossbar_link_port_read_in_to_out     (uint32_t num_port, uint32_t num_bank);
     132  public : uint32_t  partial_crossbar_link_port_read_in_to_select  (uint32_t num_port, uint32_t num_bank);
     133  public : uint32_t  partial_crossbar_link_port_write_in_to_out    (uint32_t num_port, uint32_t num_bank);
     134  public : uint32_t  partial_crossbar_link_port_write_in_to_select (uint32_t num_port, uint32_t num_bank);
     135
    121136  private : void     allocation                (void);
    122137  private : void     deallocation              (void);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/src/Parameters.cpp

    r15 r23  
    3131    _nb_port_write_by_bank (nb_port_write_by_bank),
    3232    _crossbar              (crossbar             ),
    33     _shift_address         (static_cast<uint32_t>(ceil(log2(_nb_bank))))
     33    _shift_address         (_size_address-static_cast<uint32_t>(ceil(log2(_nb_bank))))
    3434  {
    3535    log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"Parameters","Begin");
    … …  
    3939        // All port_src is connected with one port_dest on each bank
    4040       
    41         _link_port_read  = new uint32_t [_nb_port_read ];
    42         for (uint32_t i=0; i<_nb_port_read ; i++)
    43           _link_port_read  [i] = i%_nb_port_read_by_bank;
     41        _link_port_read_in_to_out          = new uint32_t [_nb_port_read ];
     42        _link_port_read_in_to_select       = new uint32_t [_nb_port_read ];
     43        _link_port_write_in_to_out         = new uint32_t [_nb_port_write];
     44        _link_port_write_in_to_select      = new uint32_t [_nb_port_write];
     45        uint32_t _nb_port_select_by_bank_read_port  [_nb_port_read_by_bank ];
     46        uint32_t _nb_port_select_by_bank_write_port [_nb_port_write_by_bank];
     47       
     48        // init
     49        for (uint32_t i=0; i<_nb_port_read_by_bank ;i++)
     50          _nb_port_select_by_bank_read_port  [i] = 0;
     51       
     52        for (uint32_t i=0; i<_nb_port_read         ;i++)
     53          {
     54            uint32_t x = i%_nb_port_read_by_bank;
     55            _link_port_read_in_to_out          [i] = x;
     56            _link_port_read_in_to_select       [i] = _nb_port_select_by_bank_read_port [x];
     57            _nb_port_select_by_bank_read_port  [x] ++;
     58          }
    4459
    45         _link_port_write = new uint32_t [_nb_port_write];
    46         for (uint32_t i=0; i<_nb_port_write; i++)
    47           _link_port_write [i] = i%_nb_port_write_by_bank;
     60        // init
     61        for (uint32_t i=0; i<_nb_port_write_by_bank ;i++)
     62          _nb_port_select_by_bank_write_port [i] = 0;
     63       
     64        for (uint32_t i=0; i<_nb_port_write         ;i++)
     65          {
     66            uint32_t x = i%_nb_port_write_by_bank;
     67            _link_port_write_in_to_out         [i] = x;
     68            _link_port_write_in_to_select      [i] = _nb_port_select_by_bank_write_port [x];
     69            _nb_port_select_by_bank_write_port [x] ++;
     70          }
    4871      }
    4972    // else : don't allocate
    5073
    51     _nb_port_select_by_bank_read_port  = new uint32_t [_nb_port_read_by_bank ];
    52    
    53     if (_crossbar == FULL_CROSSBAR)
    54       // All port_src is connected with all port_dest on each bank
    55       for (uint32_t i=0; i<_nb_port_read_by_bank ;i++)
    56         _nb_port_select_by_bank_read_port [i] = _nb_port_read;
    57     else
    58       // All port_src is connected with one port_dest on each bank
    59       {
    60         for (uint32_t i=0; i<_nb_port_read_by_bank ;i++)
    61           _nb_port_select_by_bank_read_port [i] = 0;
    62 
    63         for (uint32_t i=0; i<_nb_port_read         ;i++)
    64           _nb_port_select_by_bank_read_port [_link_port_read [i]] ++;
    65       }
    66    
    67     _nb_port_select_by_bank_write_port = new uint32_t [_nb_port_write_by_bank];
    68 
    69     if (_crossbar == FULL_CROSSBAR)
    70       // All port_src is connected with all port_dest on each bank
    71       for (uint32_t i=0; i<_nb_port_write_by_bank ;i++)
    72         _nb_port_select_by_bank_write_port [i] = _nb_port_write;
    73     else
    74       // All port_src is connected with one port_dest on each bank
    75       {
    76         for (uint32_t i=0; i<_nb_port_write_by_bank ;i++)
    77           _nb_port_select_by_bank_write_port [i] = 0;
    78 
    79         for (uint32_t i=0; i<_nb_port_write         ;i++)
    80           _nb_port_select_by_bank_write_port [_link_port_write[i]] ++;
    81       }
    82    
    8374    test();
    8475    log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"Parameters","End");
    … …  
    9788   {
    9889    log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"Parameters (copy)","Begin");
    99 
    100     _nb_port_select_by_bank_read_port  = new uint32_t [_nb_port_read_by_bank ];
    101     for (uint32_t i=0; i<_nb_port_read_by_bank; i++)
    102       _nb_port_select_by_bank_read_port [i] = param._nb_port_select_by_bank_read_port [i];
    103    
    104     _nb_port_select_by_bank_write_port = new uint32_t [_nb_port_write_by_bank ];
    105     for (uint32_t i=0; i<_nb_port_write_by_bank; i++)
    106       _nb_port_select_by_bank_write_port[i] = param._nb_port_select_by_bank_write_port [i];
    107    
    10890    test();
    10991    log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"Parameters (copy)","End");

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/src/RegisterFile_Multi_Banked_Glue.cpp

    r15 r23  
    3333    log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"RegisterFile_Multi_Banked_Glue","Begin");
    3434
     35#ifdef SYSTEMC
     36    // write function pointer
     37    if (_crossbar == PARTIAL_CROSSBAR)
     38      {
     39        link_port_read_in_to_out     = &morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::partial_crossbar_link_port_read_in_to_out    ;
     40        link_port_read_in_to_select  = &morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::partial_crossbar_link_port_read_in_to_select ;
     41        link_port_write_in_to_out    = &morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::partial_crossbar_link_port_write_in_to_out   ;
     42        link_port_write_in_to_select = &morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::partial_crossbar_link_port_write_in_to_select;
     43      }
     44    else
     45      {
     46        link_port_read_in_to_out     = &morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::   full_crossbar_link_port_read_in_to_out    ;
     47        link_port_read_in_to_select  = &morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::   full_crossbar_link_port_read_in_to_select ;
     48        link_port_write_in_to_out    = &morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::   full_crossbar_link_port_write_in_to_out   ;
     49        link_port_write_in_to_select = &morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::RegisterFile_Multi_Banked_Glue::   full_crossbar_link_port_write_in_to_select;
     50      }
     51#endif
     52
    3553#ifdef STATISTICS
    3654    log_printf(INFO,RegisterFile_Multi_Banked_Glue,"RegisterFile_Multi_Banked_Glue","Allocation of statistics");
    … …  
    6684
    6785    allocation ();
    68 
     86   
    6987#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
    7088    log_printf(INFO,RegisterFile_Multi_Banked_Glue,"RegisterFile_Multi_Banked_Glue","Method - transition");

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/src/RegisterFile_Multi_Banked_Glue_genMealy_read_in.cpp

    r15 r23  
    99#include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/include/RegisterFile_Multi_Banked_Glue.h"
    1010
    11 namespace morpheo                    {
     11namespace morpheo {
    1212namespace behavioural {
    1313namespace generic {
    … …  
    1616namespace registerfile_multi_banked_glue {
    1717
    18  
    1918  void RegisterFile_Multi_Banked_Glue::genMealy_read_in (void)
    2019  {
    2120    log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"genMealy_read_in","Begin");
    2221   
    23     for (uint32_t l=0; l<_param._nb_port_read; l++)
     22    for (uint32_t i=0; i<_param._nb_port_read; i++)
    2423      {
    25         uint32_t num_bank = PORT_READ(in_READ_IN_ADDRESS [l])>>_param._shift_address;
     24        log_printf(ALL,RegisterFile_Multi_Banked_Glue,"genMealy_read_in","read_in [%d]",i);
    2625
     26        uint32_t num_bank        = PORT_READ(in_READ_IN_ADDRESS [i])>>_param._shift_address;
     27        uint32_t num_port_out    = *link_port_read_in_to_out    (i,num_bank);
     28        uint32_t num_port_select = *link_port_read_in_to_select (i,num_bank);
     29
     30        if (_param._crossbar == FULL_CROSSBAR)
     31          {
     32            // scearch in all possible destination the good
     33            // if not found : num_port = 0
     34            for (num_port = _param._nb_port_read_by_bank-1; num_port > 0; num_port --)
     35              {
     36                log_printf(ALL,RegisterFile_Multi_Banked_Glue,"genMealy_read_in","test read_out_port   %d",num_port);           
     37               
     38                for (uint32_t j=0; j<_param._nb_port_select_by_bank_read_port [num_port]; j++)
     39                  {
     40                log_printf(ALL,RegisterFile_Multi_Banked_Glue,"genMealy_read_in","test read_out_select %d",j);
     41                    if (PORT_READ(in_READ_SELECT_ACK [num_bank][num_port][j])==1)
     42                      goto end_FULL_CROSSBAR;
     43                  }
     44              }
     45          }
     46       
     47        end_FULL_CROSSBAR :     
     48         
     49        log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"genMealy_read_in","read_in [%d] address : %.8x - num_bank %d, num_port %d",i,static_cast<uint32_t>(PORT_READ(in_READ_IN_ADDRESS [i])),num_bank,num_port);
     50       
     51        PORT_WRITE(out_READ_IN_ACK  [i],PORT_READ(in_READ_SELECT_ACK [num_bank][num_port]));
     52        PORT_WRITE(out_READ_IN_DATA [i],PORT_READ(in_READ_OUT_DATA   [num_bank][num_port]));
    2753//      (*(out_READ_IN_ACK  [l])) (*(in_READ_IN_ADDRESS [i][j]));
    2854//      (*(out_READ_IN_DATA [l])) (*(in_READ_IN_ADDRESS [i][j]));
    29 
    30 //      for (uint32_t i=0; i<_param._nb_bank; i++)
    31 //        for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
    32 //          {
    33 //            (*(out_READ_IN_ACK  [l])) (*(in_READ_OUT_ACK      [i][j]));
    34 //            (*(out_READ_IN_DATA [l])) (*(in_READ_OUT_DATA     [i][j]));
    35 //            for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
    36 //              {
    37 //                (*(out_READ_IN_ACK  [l])) (*(in_READ_SELECT_ACK [i][j][k]));
    38 //                (*(out_READ_IN_DATA [l])) (*(in_READ_SELECT_ACK [i][j][k]));
    39 //              }
    40 //          }
    4155      }
    4256

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile

    r15 r23  
    2424
    2525include                         ../Makefile.deps
    26 include                         $(DIR_MORPHEO)/Behavioural/Makefile.defs
     26include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
    2727include                         $(DIR_MORPHEO)/Behavioural/Makefile.Common
    2828include                         $(DIR_MORPHEO)/Behavioural/Makefile.Selftest
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