Changeset 23 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp
- Timestamp:
- May 21, 2007, 12:01:51 PM (17 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp
r15 r23 9 9 #define NB_ITERATION 16 10 10 11 #define TEXT(str) do {cout << "<" << name << "> : " << str << endl;} while (0) 11 12 #define LABEL(str) do {cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; _RegisterFile_Multi_Banked_Glue->vhdl_testbench_label(str);} while (0) 12 13 … … 18 19 morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::Parameters _param) 19 20 { 20 cout << "<" << name << "> : Simulation SystemC" << endl;21 TEXT("Simulation SystemC"); 21 22 22 23 RegisterFile_Multi_Banked_Glue * _RegisterFile_Multi_Banked_Glue = new RegisterFile_Multi_Banked_Glue (name.c_str(), … … 192 193 ********************************************************/ 193 194 194 cout << "<" << name << "> Instanciation of _RegisterFile_Multi_Banked_Glue" << endl;195 TEXT("Instanciation of _RegisterFile_Multi_Banked_Glue"); 195 196 196 197 (*(_RegisterFile_Multi_Banked_Glue->in_CLOCK)) (*(CLOCK)); … … 247 248 248 249 249 cout << "<" << name << "> Start Simulation ............" << endl;250 TEXT("Start Simulation ............"); 250 251 251 252 /******************************************************** … … 265 266 266 267 uint32_t read_in_num_bank [_param._nb_port_read]; // Number of bank 267 //Tcontrol_t read_in_valid [_param._nb_port_read]; 268 Tcontrol_t read_is_busy [_param._nb_port_read]; 269 bool read_out_find [_param._nb_bank][_param._nb_port_read_by_bank]; 270 uint32_t read_out_port [_param._nb_bank][_param._nb_port_read_by_bank]; 271 268 272 Tcontrol_t read_in_ack [_param._nb_port_read]; // to test 269 273 Tdata_t read_in_data [_param._nb_port_read]; // to test 270 274 Tcontrol_t read_out_val [_param._nb_bank][_param._nb_port_read_by_bank]; 271 Tcontrol_t read_out_ack [_param._nb_bank][_param._nb_port_read_by_bank];272 275 Taddress_t read_out_address [_param._nb_bank][_param._nb_port_read_by_bank]; 273 Tcontrol_t read_is_busy [_param._nb_port_read]; 274 Tcontrol_t read_select_val [_param._nb_bank][_param._nb_port_read ]; 275 Tcontrol_t read_select_ack [_param._nb_bank][_param._nb_port_read ]; 276 Tcontrol_t read_select_val [_param._nb_bank][_param._nb_port_read_by_bank][_param._nb_port_read]; 276 277 277 278 LABEL("Loop of Test"); … … 281 282 LABEL("Iteration "+toString(iteration)); 282 283 283 LABEL("Test read_in");284 //LABEL("Test read_in"); 284 285 285 286 // Write in interface "read_in" … … 287 288 { 288 289 read_in_num_bank [i] = rand() % _param._nb_bank; 289 Tcontrol_t read_in_val id= (rand() % 2) != 0;290 Tcontrol_t read_in_val = (rand() % 2) != 0; 290 291 291 292 Taddress_t address = (read_in_num_bank[i] << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i); 292 293 293 read_is_busy [i] = (read_in_valid == 0); 294 read_in_ack [i] = 0; 295 read_in_data [i] = 0; 296 READ_IN_VAL [i]->write(read_in_valid); 297 READ_IN_ADDRESS [i]->write(address); 298 299 for (uint32_t j=0; j<_param._nb_bank; j++) 300 read_select_ack [j][i] = 0; 294 read_is_busy [i] = (read_in_val == 0); // invalid = busy 295 read_in_ack [i] = 0; // init 296 read_in_data [i] = 0; // init 297 READ_IN_VAL [i]->write(read_in_val); // write signal 298 READ_IN_ADDRESS [i]->write(address); // write signal 301 299 } 302 300 303 for (uint32_t i=0; i<_param._nb_bank; i++)304 for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)305 {306 read_out_ack [i][j] = (rand() % 2) != 0;307 READ_OUT_ACK [i][j]->write(read_out_ack [i][j]);308 READ_OUT_DATA [i][j]->write((j<<1)|1); // (j<<1)|1 afin de n'avoir jamais 0309 }310 311 301 // compute the good read_select 312 302 for (uint32_t i=0; i<_param._nb_bank; i++) 313 303 for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) 314 304 { 305 Tcontrol_t read_out_ack = (rand() % 2) != 0; 306 READ_OUT_ACK [i][j]->write(read_out_ack); 307 READ_OUT_DATA [i][j]->write((j<<1)|1); // (j<<1)|1 afin de n'avoir jamais 0 308 309 read_out_find [i][j] = false; 310 read_out_port [i][j] = 0; 311 312 read_out_val [i][j] = 0; 313 read_out_address [i][j] = 0; 314 315 315 bool find = false; // have find a port_in to link with this port_out 316 316 for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++) 317 317 { 318 319 318 uint32_t num_port; // number of port 320 319 … … 323 322 num_port = k; 324 323 else 325 num_port = _param._link_port_read [i];326 327 read_select_val [i][ num_port] = read_out_ack [i][j] && not read_is_busy [num_port];328 329 if ((read_out_ack [i][j] == 0) || find) 330 read_select_ack [i][num_port] = 0; // read_out is busy or alreadyfind331 else324 num_port = k*_param._nb_port_read_by_bank+j; 325 326 read_select_val [i][j][k] = read_out_ack and not read_is_busy [num_port] and (read_in_num_bank[num_port] == i); // select val if port is not busy and out accept a data 327 Tcontrol_t read_select_ack = 0; 328 329 // test a previous find 330 if (not ((read_out_ack == 0) || find)) 332 331 { 333 332 // find a busy port? 334 find = not read_is_busy [num_port];335 read_is_busy [num_port]|= find;336 read_select_ack [i][num_port] = find;333 find = read_select_val; 334 read_is_busy [num_port]|= find; // port became busy if find 335 read_select_ack = find; // ack if find 337 336 338 337 if (find) 339 338 { 339 read_out_find [i][j] = true; 340 read_out_port [i][j] = num_port; 341 342 // know the good output 340 343 read_in_ack [num_port] = 1; 341 344 read_in_data [num_port] = ((j<<1)|1); 342 345 read_out_val [i][j] = 1; 343 read_out_address [i][j] = ( read_in_num_bank[i] << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i);346 read_out_address [i][j] = (i << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & num_port); 344 347 } 345 348 } 346 349 347 READ_SELECT_ACK [i][j][k]->write(read_select_ack [i][num_port]);350 READ_SELECT_ACK [i][j][k]->write(read_select_ack); 348 351 } 349 352 } … … 352 355 sc_start(1); 353 356 354 // // lot of test 355 // public : SC_OUT(Tcontrol_t) ** out_READ_IN_ACK ; 356 // public : SC_OUT(Tdata_t ) ** out_READ_IN_DATA ; 357 358 // public : SC_OUT(Tcontrol_t) **** out_READ_SELECT_VAL ; 359 360 // public : SC_OUT(Tcontrol_t) *** out_READ_OUT_VAL ; 361 // public : SC_OUT(Taddress_t) *** out_READ_OUT_ADDRESS ; 357 // test output 358 359 TEXT ("===== Test Output ====="); 360 for (uint32_t i=0; i<_param._nb_port_read; i++) 361 { 362 TEXT ("Read_in [" << i << "] : " 363 << READ_IN_VAL [i]->read() << "," 364 << read_in_ack [i] << " - " 365 << "Reg[" << READ_IN_ADDRESS [i]->read() << "] -> " 366 << read_in_data [i] << " " 367 << "{bank : " << read_in_num_bank[i] << "}" 368 ); 369 370 TEST (Tcontrol_t, read_in_ack [i], READ_IN_ACK [i]->read()); 371 if (READ_IN_VAL [i]->read() and READ_IN_ACK [i]->read()) 372 TEST (Tdata_t , read_in_data [i], READ_IN_DATA [i]->read()); 373 } 374 375 cout << endl; 376 for (uint32_t i=0; i<_param._nb_bank; i++) 377 for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) 378 { 379 TEXT ("Read_out [" << i << "][" << j << "] : " 380 << read_out_val [i][j] << "," 381 << READ_OUT_ACK [i][j]->read() << " - " 382 << "Reg[" << read_out_address [i][j] << "] -> " 383 << READ_OUT_DATA [i][j]->read() << " - " 384 << "[" << read_out_find [i][j]<< " , " 385 << read_out_port [i][j] << "]" 386 ); 387 388 TEST (Tcontrol_t, read_out_val [i][j], READ_OUT_VAL [i][j]->read()); 389 if (READ_OUT_VAL [i][j]->read() and READ_OUT_ACK [i][j]->read()) 390 TEST (Taddress_t, read_out_address [i][j], READ_OUT_ADDRESS [i][j]->read()); 391 392 for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++) 393 { 394 uint32_t num_port; // number of port 395 396 // compute the good number of port 397 if (_param._crossbar == FULL_CROSSBAR) 398 num_port = k; 399 else 400 num_port = k*_param._nb_port_read_by_bank+j; 401 402 TEXT (" * Read_select [" << i << "][" << j << "][" << k << "] : " 403 << read_select_val [i][j][k] << "," 404 << READ_SELECT_ACK [i][j][k]->read() << " - " 405 << "link with read_in[" << num_port << "]" 406 ); 407 408 TEST (Tcontrol_t, read_select_val [i][j][k], READ_SELECT_VAL [i][j][k]->read()); 409 } 410 411 412 413 } 362 414 363 415 } 416 417 sc_start(0); 364 418 365 419 /******************************************************** … … 367 421 ********************************************************/ 368 422 369 cout << "<" << name << "> ............ Stop Simulation" << endl;423 TEXT("............ Stop Simulation"); 370 424 371 425 delete CLOCK; 372 426 427 TEXT("delete read_in"); 373 428 for (uint32_t i=0; i<_param._nb_port_read; i++) 374 429 { 430 // TEXT("1, i " << i); 375 431 delete READ_IN_VAL [i]; 432 // TEXT("2"); 376 433 delete READ_IN_ACK [i]; 434 // TEXT("3"); 377 435 delete READ_IN_ADDRESS [i]; 436 // TEXT("4"); 378 437 delete READ_IN_DATA [i]; 438 // TEXT("5"); 379 439 } 380 440 … … 384 444 delete READ_IN_DATA ; 385 445 446 TEXT("delete read_select"); 386 447 for (uint32_t i=0; i<_param._nb_bank; i++) 387 448 { … … 402 463 delete READ_SELECT_ACK; 403 464 465 TEXT("delete read_out"); 404 466 for (uint32_t i=0; i<_param._nb_bank; i++) 405 467 { … … 423 485 delete READ_OUT_DATA ; 424 486 487 TEXT("delete write_in"); 425 488 for (uint32_t i=0; i<_param._nb_port_write; i++) 426 489 { … … 436 499 delete WRITE_IN_DATA ; 437 500 501 TEXT("delete write_select"); 438 502 for (uint32_t i=0; i<_param._nb_bank; i++) 439 503 { … … 454 518 delete WRITE_SELECT_ACK; 455 519 520 TEXT("delete write_out"); 456 521 for (uint32_t i=0; i<_param._nb_bank; i++) 457 522 { … … 477 542 #endif 478 543 544 479 545 delete _RegisterFile_Multi_Banked_Glue; 480 546 }
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