Changeset 40 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis

Timestamp:

Jun 5, 2007, 11:06:46 PM (17 years ago)

Author:

rosiere

Message:

Interface et Signal, c'est deux classes enregistres la valeurs des signaux à chaque cycle ... étape préparatoire avan le changement de la classe Vhdl_Testbench

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis (modified) (3 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis

@@ -60 +60 @@
 $(DIR_LOG)/%.fpga.log           : 
                                 @$(ECHO) "Synthetis on FPGA  : $*"
-                                @$(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc > $@
+                                @$(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@
 
 $(DIR_WORK)                     :
@@ -67 +67 @@
 
 $(DIR_LOG)/%.vhdl_sim.log       : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log
-                                @$(ECHO) "VHDL's Simulation: $*"
-                                @$(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* |$(UPPERtoLOWER)`" > $@
+                                @$(ECHO) "VHDL's Simulation  : $*"
+                                @$(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* |$(UPPERtoLOWER)`" &> $@
                                 declare -i count=`$(GREP) -ch "Test KO" $@`;            \
                                 if $(TEST) $$count -eq 0;                               \
@@ -77 +77 @@
 $(DIR_LOG)/%.vhdl.log           : $(DIR_VHDL)/%.vhdl
                                 @$(ECHO) "VHDL's Compilation : $*"
-                                @$(MODELTECH_VCOM) $< > $@
+                                @$(MODELTECH_VCOM) $< &> $@
 
 synthesis_clean                 :