Ignore:
Timestamp:
Jun 5, 2007, 11:06:46 PM (17 years ago)
Author:
rosiere
Message:

Interface et Signal, c'est deux classes enregistres la valeurs des signaux à chaque cycle ... étape préparatoire avan le changement de la classe Vhdl_Testbench

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface.cpp

    r38 r40  
    2020    log_printf(FUNC,Behavioural,"Interface","Begin");
    2121
    22     _comment     = "";
    23     _list_signal = new (list<Signal*>);
     22    _comment       = "";
     23    _list_signal   = new (list<Signal*>);
    2424
    2525#ifdef POSITION
    26      _is_map        = false;
    27      _entity_map    = NULL;
    28      _interface_map = NULL;
     26    _is_map        = false;
     27    _entity_map    = NULL;
     28    _interface_map = NULL;
     29#endif
     30
     31#ifdef VHDL_TESTBENCH
     32    _list_cycle    = new list<string>;
    2933#endif
    3034
     
    4549    _interface_map = interface._interface_map;
    4650#endif
     51#ifdef VHDL_TESTBENCH
     52    _list_cycle    = interface._list_cycle;
     53#endif
     54
    4755    log_printf(FUNC,Behavioural,"Interface (copy)","End");
    4856  };
     
    5462    if (_list_signal->empty()== false)
    5563      {
    56         list<Signal*>::iterator i     = _list_signal->begin();
     64        list<Signal*>::iterator i = _list_signal->begin();
    5765
    5866        while (i != _list_signal->end())
     
    6472
    6573    delete _list_signal;
     74
     75#ifdef VHDL_TESTBENCH
     76    delete _list_cycle ;
     77#endif
     78
    6679    log_printf(FUNC,Behavioural,"~Interface","End");
    6780  };
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