Ignore:
Timestamp:
Jun 7, 2007, 9:13:47 PM (17 years ago)
Author:
rosiere
Message:

Vhdl_Testbench : Modification du testbench. Maintenant complétement encapsuler dans la classe "Interfaces".
Suppression de la class Vhdl_Testbench dans un avenir proche :D
Suppression du répertoire Configuration.old

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src
Files:
1 deleted
3 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component.cpp

    r40 r41  
    4444#endif
    4545
    46 #ifdef VHDL_TESTBENCH
    47     log_printf(INFO,@COMPONENT,"@COMPONENT","Creation of a testbench");
    48 
    49     _vhdl_testbench = new Vhdl_Testbench (_name);
    50 #endif
    51 
    5246#ifdef VHDL
    5347    // generate the vhdl
     
    7872    log_printf(FUNC,@COMPONENT,"~@COMPONENT","Begin");
    7973
    80 #ifdef VHDL_TESTBENCH
    81     log_printf(INFO,@COMPONENT,"~@COMPONENT","Generate Testbench  file");
    82 
    83     // generate the test bench
    84     _vhdl_testbench->generate_file();
    85     delete _vhdl_testbench;
    86 #endif
    87 
    8874#ifdef STATISTICS
    8975    log_printf(INFO,@COMPONENT,"~@COMPONENT","Generate Statistics file");
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_port.cpp

    r40 r41  
    1919    _interfaces->set_port(vhdl);
    2020
    21 #ifdef VHDL_TESTBENCH
    22     _interfaces->set_port(_vhdl_testbench);                     
    23    _vhdl_testbench->set_clock    ("in_CLOCK",true);
    24 #endif   
    25 
    2621    log_printf(FUNC,@COMPONENT,"vhdl_port","End");
    2722  };
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_testbench_transition.cpp

    r40 r41  
    2020    sc_start(0);
    2121
    22     _interfaces->testbench(_vhdl_testbench);
    23    
    24     // add_test :
    25     //  - True  : the cycle must be compare with the output of systemC
    26     //  - False : no test
    27     _vhdl_testbench->add_test(true);
    28 
    29     _vhdl_testbench->new_cycle (); // always at the end
     22    _interfaces->testbench();
    3023
    3124    log_printf(FUNC,@COMPONENT,"vhdl_testbench_transition","End");
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