- Timestamp:
- Jun 7, 2007, 9:13:47 PM (17 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface.h
r40 r41 21 21 #ifdef VHDL 22 22 #include "Behavioural/include/Vhdl.h" 23 #endif24 #ifdef VHDL_TESTBENCH25 #include "Behavioural/include/Vhdl_Testbench.h"26 23 #endif 27 24 #include "Include/ToString.h" … … 53 50 54 51 #ifdef VHDL_TESTBENCH 55 private : list<string> * _list_cycle;52 private : uint32_t _nb_cycle ; 56 53 #endif 57 54 … … 80 77 public : sc_in_clk * set_signal_clk (string name , 81 78 uint32_t size , 82 presence_port_t presence_port= PORT_VHDL_YES_TESTBENCH_YES)79 presence_port_t presence_port=CLOCK_VHDL_YES) 83 80 { 84 81 log_printf(FUNC,Behavioural,"set_signal_clk","Begin"); 85 82 86 Signal * sig = set_signal (name, IN , size, presence_port); 83 if ((presence_port != CLOCK_VHDL_YES) and 84 (presence_port != CLOCK_VHDL_NO )) 85 throw ErrorMorpheo ("Signal \""+name+"\" is a clock, bad presence_port."); 86 87 Signal * sig = set_signal (name, IN , size, presence_port); 87 88 sc_in_clk * signal = new sc_in_clk (sig->_name.c_str()); 88 89 … … 98 99 { 99 100 log_printf(FUNC,Behavioural,"set_signal_in","Begin"); 101 102 if ((presence_port == CLOCK_VHDL_YES) or 103 (presence_port == CLOCK_VHDL_NO )) 104 throw ErrorMorpheo ("Signal \""+name+"\" is not a clock, bad presence_port."); 100 105 101 106 Signal * sig = set_signal (name, IN , size, presence_port); … … 117 122 log_printf(FUNC,Behavioural,"set_signal_out","Begin"); 118 123 124 if ((presence_port == CLOCK_VHDL_YES) or 125 (presence_port == CLOCK_VHDL_NO )) 126 throw ErrorMorpheo ("Signal \""+name+"\" is not a clock, bad presence_port."); 127 119 128 Signal * sig = set_signal (name, OUT , size, presence_port); 120 129 sc_out <T> * port = new sc_out <T> (sig->_name.c_str()); … … 131 140 #ifdef VHDL 132 141 public : void set_port (Vhdl * & vhdl); 142 #ifdef VHDL_TESTBENCH 143 public : void set_signal (Vhdl * & vhdl); 144 public : void get_signal (list<string> * & list_signal); 145 #endif 133 146 #endif 134 147 #ifdef VHDL_TESTBENCH 135 public : void set_port (Vhdl_Testbench * & vhdl_testbench); 148 public : uint32_t get_cycle (void); 149 public : string get_clock (void); 150 151 public : void testbench (void); 152 public : void testbench_cycle (void); 153 public : void testbench_body (Vhdl * & vhdl , 154 string counter_name ); 155 public : string testbench_test (Vhdl * & vhdl , 156 string counter_name); 157 public : string testbench_test_ok (Vhdl * & vhdl ); 158 protected : string testbench_test_name (Vhdl * & vhdl); 159 protected : string testbench_test_ok_name(Vhdl * & vhdl); 160 136 161 #endif 137 162 … … 139 164 public : void port_map (void * entity, 140 165 void * interface); 141 #endif142 143 #ifdef VHDL_TESTBENCH144 public : void testbench_cycle (void);145 public : void testbench (Vhdl_Testbench * & vhdl_testbench);146 166 #endif 147 167
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