Changeset 42 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src
- Timestamp:
- Jul 5, 2007, 5:50:19 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src
- Files:
-
- 2 deleted
- 9 edited
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Branch_History_Table.cpp (modified) (4 diffs)
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Branch_History_Table_allocation.cpp (modified) (3 diffs)
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Branch_History_Table_deallocation.cpp (modified) (1 diff)
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Branch_History_Table_vhdl.cpp (modified) (2 diffs)
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Branch_History_Table_vhdl_body.cpp (modified) (2 diffs)
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Branch_History_Table_vhdl_port.cpp (modified) (1 diff)
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Branch_History_Table_vhdl_signal.cpp (modified) (1 diff)
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Branch_History_Table_vhdl_testbench_label.cpp (deleted)
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Branch_History_Table_vhdl_testbench_port.cpp (deleted)
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Branch_History_Table_vhdl_testbench_transition.cpp (modified) (1 diff)
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Branch_History_Table_vhdl_type.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table.cpp
r15 r42 32 32 #endif 33 33 { 34 35 #ifdef SYSTEMC 36 allocation (); 37 #endif 38 34 39 #ifdef STATISTICS 35 40 // Allocation of statistics … … 39 44 #endif 40 45 41 #ifdef VHDL_TESTBENCH42 // Creation of a testbench43 // -> port44 // -> clock's signals45 _vhdl_testbench = new Vhdl_Testbench (_name);46 vhdl_testbench_port ();47 _vhdl_testbench->set_clock ("in_CLOCK",true);48 #endif49 50 46 #ifdef VHDL 51 47 // generate the vhdl … … 53 49 #endif 54 50 51 55 52 #ifdef SYSTEMC 56 allocation ();57 58 53 // // Constant 59 54 // for (uint32_t i=0; i<_param._nb_prediction ; i++) … … 77 72 Branch_History_Table::~Branch_History_Table (void) 78 73 { 79 #ifdef VHDL_TESTBENCH80 // generate the test bench81 _vhdl_testbench->generate_file();82 delete _vhdl_testbench;83 #endif84 85 74 #ifdef STATISTICS 86 75 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_allocation.cpp
r15 r42 20 20 void Branch_History_Table::allocation (void) 21 21 { 22 string rename; 23 24 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 25 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 26 22 _component = new Component (); 23 24 Entity * entity = _component->set_entity (_name 25 ,"Branch_History_Table" 26 #ifdef POSITION 27 ,MIXTE 28 #endif 29 ); 30 31 _interfaces = entity->set_interfaces(); 32 33 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 34 { 35 Interface * interface = _interfaces->set_interface("" 36 #ifdef POSITION 37 , IN 38 , SOUTH 39 , "Generalist interface" 40 #endif 41 ); 42 43 in_CLOCK = interface->set_signal_clk ("clock" ,1); 44 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_YES); 45 } 46 47 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 27 48 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; 28 49 out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction]; … … 32 53 for (uint32_t i=0; i<_param._nb_prediction; i++) 33 54 { 34 rename = "in_PREDICT_VAL[" +toString(i)+"]"; 35 in_PREDICT_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 36 37 rename = "out_PREDICT_ACK[" +toString(i)+"]"; 38 out_PREDICT_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 39 40 rename = "in_PREDICT_ADDRESS["+toString(i)+"]"; 41 in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 42 43 rename = "out_PREDICT_HISTORY["+toString(i)+"]"; 44 out_PREDICT_HISTORY [i] = new SC_OUT(Thistory_t) (rename.c_str()); 45 } 46 47 in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 48 out_BRANCH_COMPLETE_ACK = new SC_OUT (Tcontrol_t) * [_param._nb_branch_complete]; 49 in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; 50 in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete]; 51 in_BRANCH_COMPLETE_DIRECTION= new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 52 signal_BRANCH_COMPLETE_HISTORY = new SC_SIGNAL (Thistory_t) * [_param._nb_branch_complete]; 55 Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) 56 #ifdef POSITION 57 , IN 58 , WEST 59 , "Interface Predict" 60 #endif 61 ); 62 63 in_PREDICT_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 64 out_PREDICT_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 65 in_PREDICT_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 66 out_PREDICT_HISTORY [i] = interface->set_signal_out <Thistory_t> ("history", _param._size_shifter); 67 } 68 69 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 70 71 in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 72 out_BRANCH_COMPLETE_ACK = new SC_OUT (Tcontrol_t) * [_param._nb_branch_complete]; 73 in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; 74 in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete]; 75 in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 53 76 54 77 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 55 78 { 56 rename = "in_BRANCH_COMPLETE_VAL[" +toString(i)+"]"; 57 in_BRANCH_COMPLETE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 58 59 rename = "out_BRANCH_COMPLETE_ACK[" +toString(i)+"]"; 60 out_BRANCH_COMPLETE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 61 62 rename = "in_BRANCH_COMPLETE_ADDRESS["+toString(i)+"]"; 63 in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 64 65 rename = "in_BRANCH_COMPLETE_HISTORY["+toString(i)+"]"; 66 in_BRANCH_COMPLETE_HISTORY [i] = new SC_IN (Thistory_t) (rename.c_str()); 67 68 rename = "in_BRANCH_COMPLETE_DIRECTION[" +toString(i)+"]"; 69 in_BRANCH_COMPLETE_DIRECTION[i] = new SC_IN (Tcontrol_t) (rename.c_str()); 70 71 rename = "signal_BRANCH_COMPLETE_HISTORY["+toString(i)+"]"; 72 signal_BRANCH_COMPLETE_HISTORY [i] = new SC_SIGNAL (Thistory_t) (rename.c_str()); 73 79 Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) 80 #ifdef POSITION 81 , IN 82 , EAST 83 , "Interface branch complete" 84 #endif 85 ); 86 87 in_BRANCH_COMPLETE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 88 out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 89 in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address" , static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 90 in_BRANCH_COMPLETE_HISTORY [i] = interface->set_signal_in <Thistory_t> ("history" , _param._size_shifter); 91 in_BRANCH_COMPLETE_DIRECTION [i] = interface->set_signal_in <Tcontrol_t> ("direction", 1); 74 92 } 75 93 76 94 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 77 95 string name_component; 96 78 97 // =====[ component_Shifter ]========================================= 79 98 80 99 name_component = _name+"_Shifter"; 81 100 82 component_Shifter = new morpheo::behavioural::generic::shifter::Shifter (name_component.c_str() ,101 component_Shifter = new morpheo::behavioural::generic::shifter::Shifter (name_component.c_str() 83 102 #ifdef STATISTICS 84 _param_statistics , 85 #endif 86 *(_param._param_shifter) ); 87 88 89 // Instantiation 90 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 91 (*(component_Shifter->in_CLOCK)) (*(in_CLOCK)); 92 #endif 93 94 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 95 { 96 (*(component_Shifter-> in_SHIFTER_DATA [i])) (*( in_BRANCH_COMPLETE_HISTORY [i])); 97 (*(component_Shifter-> in_SHIFTER_CARRY_IN [i])) (*( in_BRANCH_COMPLETE_DIRECTION[i])); 98 (*(component_Shifter->out_SHIFTER_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); 99 } 100 103 ,_param_statistics 104 #endif 105 ,*(_param._param_shifter)); 106 107 _component->set_component (component_Shifter->_component 108 #ifdef POSITION 109 , 25 110 , 25 111 , 10 112 , 10 113 #endif 114 ); 115 101 116 // =====[ component_RegisterFile ]==================================== 102 117 … … 105 120 component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic(name_component.c_str(), 106 121 #ifdef STATISTICS 107 _param_statistics , 108 #endif 109 *(_param._param_registerfile)); 122 _param_statistics , 123 #endif 124 *(_param._param_registerfile)); 125 126 _component->set_component (component_RegisterFile->_component 127 #ifdef POSITION 128 , 75 129 , 75 130 , 10 131 , 10 132 #endif 133 ); 110 134 111 // Instantiation 112 (*(component_RegisterFile->in_CLOCK )) (*(in_CLOCK )); 113 (*(component_RegisterFile->in_NRESET)) (*(in_NRESET)); 135 // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 136 137 // =====[ component_RegisterFile - Instanciation ]==================== 138 139 #ifdef POSITION 140 _component->interface_map (_name+"_RegisterFile","", 141 _name ,""); 142 #endif 143 144 _component->port_map(_name+"_RegisterFile", "in_CLOCK" , _name,"in_CLOCK" ); 145 _component->port_map(_name+"_RegisterFile", "in_NRESET", _name,"in_NRESET"); 114 146 115 147 for (uint32_t i=0; i<_param._nb_prediction; i++) 116 148 { 117 (*(component_RegisterFile-> in_READ_VAL [i])) (*( in_PREDICT_VAL [i])); 118 (*(component_RegisterFile->out_READ_ACK [i])) (*(out_PREDICT_ACK [i])); 119 (*(component_RegisterFile-> in_READ_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 120 (*(component_RegisterFile->out_READ_DATA [i])) (*(out_PREDICT_HISTORY [i])); 149 #ifdef POSITION 150 _component->interface_map (_name+"_RegisterFile","read_" +toString(i), 151 _name ,"predict_"+toString(i)); 152 #endif 153 154 _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_VAL" , _name, "in_PREDICT_"+toString(i)+"_VAL" ); 155 _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_ACK" , _name,"out_PREDICT_"+toString(i)+"_ACK" ); 156 _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_ADDRESS", _name, "in_PREDICT_"+toString(i)+"_ADDRESS"); 157 _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_DATA" , _name,"out_PREDICT_"+toString(i)+"_HISTORY"); 121 158 } 122 159 123 160 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 124 161 { 125 (*(component_RegisterFile-> in_WRITE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 126 (*(component_RegisterFile->out_WRITE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 127 (*(component_RegisterFile-> in_WRITE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 128 (*(component_RegisterFile-> in_WRITE_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); 129 } 162 #ifdef POSITION 163 _component->interface_map (_name+"_RegisterFile","write_" +toString(i), 164 _name+"_Shifter" ,"shifter_"+toString(i)); 165 #endif 166 167 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); 168 _component->port_map(_name+"_RegisterFile","out_WRITE_"+toString(i)+"_ACK" , _name ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" ); 169 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_ADDRESS", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); 170 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA" , _name+"_Shifter","out_SHIFTER_" +toString(i)+"_DATA"); 171 } 172 173 // =====[ component_Shifter - Instanciation ]========================= 174 175 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 176 177 #ifdef POSITION 178 _component->interface_map (_name+"_Shifter","", 179 _name ,""); 180 #endif 181 182 _component->port_map(_name+"_Shifter", "in_CLOCK" , _name,"in_CLOCK" ); 183 _component->port_map(_name+"_Shifter", "in_NRESET", _name,"in_NRESET"); 184 185 #endif 186 187 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 188 { 189 #ifdef POSITION 190 _component->interface_map (_name+"_Shifter","shifter_"+toString(i), 191 _name ,"branch_complete_"+toString(i)); 192 193 #endif 194 195 _component->port_map(_name+"_Shifter", "in_SHIFTER_" +toString(i)+"_DATA" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"); 196 _component->port_map(_name+"_Shifter", "in_SHIFTER_" +toString(i)+"_CARRY_IN", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); 197 _component->port_map(_name+"_Shifter", "out_SHIFTER_"+toString(i)+"_DATA" , _name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA"); 198 } 199 200 #ifdef POSITION 201 _component->generate_file(); 202 #endif 130 203 }; 131 204 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_deallocation.cpp
r15 r42 19 19 void Branch_History_Table::deallocation (void) 20 20 { 21 delete in_CLOCK;22 delete in_NRESET;21 delete in_CLOCK; 22 delete in_NRESET; 23 23 24 for (uint32_t i=0; i<_param._nb_prediction; i++) 25 { 26 delete in_PREDICT_VAL [i]; 27 delete out_PREDICT_ACK [i]; 28 delete in_PREDICT_ADDRESS [i]; 29 delete out_PREDICT_HISTORY [i]; 30 } 24 delete [] in_PREDICT_VAL ; 25 delete [] out_PREDICT_ACK ; 26 delete [] in_PREDICT_ADDRESS; 27 delete [] out_PREDICT_HISTORY; 31 28 32 delete in_PREDICT_VAL ; 33 delete out_PREDICT_ACK ; 34 delete in_PREDICT_ADDRESS; 35 delete out_PREDICT_HISTORY; 36 37 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 38 { 39 delete in_BRANCH_COMPLETE_VAL [i]; 40 delete out_BRANCH_COMPLETE_ACK [i]; 41 delete in_BRANCH_COMPLETE_ADDRESS [i]; 42 delete in_BRANCH_COMPLETE_HISTORY [i]; 43 delete in_BRANCH_COMPLETE_DIRECTION[i]; 44 } 45 delete in_BRANCH_COMPLETE_VAL ; 46 delete out_BRANCH_COMPLETE_ACK ; 47 delete in_BRANCH_COMPLETE_ADDRESS; 48 delete in_BRANCH_COMPLETE_HISTORY; 49 delete in_BRANCH_COMPLETE_DIRECTION; 29 delete [] in_BRANCH_COMPLETE_VAL ; 30 delete [] out_BRANCH_COMPLETE_ACK ; 31 delete [] in_BRANCH_COMPLETE_ADDRESS; 32 delete [] in_BRANCH_COMPLETE_HISTORY; 33 delete [] in_BRANCH_COMPLETE_DIRECTION; 50 34 51 35 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 52 36 delete component_Shifter; 53 37 delete component_RegisterFile; 38 39 delete _component; 54 40 }; 55 41 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl.cpp
r2 r42 21 21 void Branch_History_Table::vhdl (void) 22 22 { 23 Vhdl vhdl (_name);23 Vhdl * vhdl = new Vhdl (_name); 24 24 25 vhdl .set_library_work (_name + "_Pack");26 vhdl .set_library_work (_name + "_RegisterFile_Pack");27 vhdl .set_library_work (_name + "_Shifter_Pack");25 vhdl->set_library_work (_name + "_Pack"); 26 vhdl->set_library_work (_name + "_RegisterFile_Pack"); 27 vhdl->set_library_work (_name + "_Shifter_Pack"); 28 28 29 29 vhdl_port (vhdl); … … 32 32 vhdl_body (vhdl); 33 33 34 vhdl.generate_file(); 34 vhdl->generate_file(); 35 36 delete vhdl; 35 37 }; 36 38 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp
r15 r42 18 18 19 19 20 void Branch_History_Table::vhdl_body (Vhdl & vhdl)20 void Branch_History_Table::vhdl_body (Vhdl * & vhdl) 21 21 { 22 // vhdl .set_body ("-- Output : always at '1'");22 // vhdl->set_body ("-- Output : always at '1'"); 23 23 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 24 // vhdl .set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");24 // vhdl->set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';"); 25 25 // for (uint32_t i=0; i<_param._nb_prediction ; i++) 26 // vhdl .set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';");27 // vhdl .set_body ("");26 // vhdl->set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); 27 // vhdl->set_body (""); 28 28 29 29 list<string> list_port_map; … … 31 31 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 32 32 { 33 vhdl .set_body_component_port_map (list_port_map," in_SHIFTER_DATA_"+toString(i)+" "," in_BRANCH_COMPLETE_HISTORY_"+toString(i));34 vhdl .set_body_component_port_map (list_port_map," in_SHIFTER_CARRY_IN_"+toString(i)+" "," in_BRANCH_COMPLETE_DIRECTION_"+toString(i));35 vhdl .set_body_component_port_map (list_port_map,"out_SHIFTER_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));33 vhdl->set_body_component_port_map (list_port_map," in_SHIFTER_"+toString(i)+"_DATA "," in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" ); 34 vhdl->set_body_component_port_map (list_port_map," in_SHIFTER_"+toString(i)+"_CARRY_IN "," in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); 35 vhdl->set_body_component_port_map (list_port_map,"out_SHIFTER_"+toString(i)+"_DATA ","signal_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" ); 36 36 } 37 37 38 vhdl .set_body_component ("component_Shifter",_name+"_Shifter",list_port_map);38 vhdl->set_body_component ("component_Shifter",_name+"_Shifter",list_port_map); 39 39 40 40 list_port_map.clear(); 41 vhdl .set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK");42 vhdl .set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET");41 vhdl->set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); 42 vhdl->set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 43 43 44 44 for (uint32_t i=0; i<_param._nb_prediction; i++) 45 45 { 46 vhdl .set_body_component_port_map (list_port_map," in_READ_VAL_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i));47 vhdl .set_body_component_port_map (list_port_map,"out_READ_ACK_"+toString(i)+" ","out_PREDICT_ACK_"+toString(i));48 vhdl .set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i));49 vhdl .set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+" ","out_PREDICT_HISTORY_"+toString(i));46 vhdl->set_body_component_port_map (list_port_map," in_READ_"+toString(i)+"_VAL "," In_PREDICT_"+toString(i)+"_VAL"); 47 vhdl->set_body_component_port_map (list_port_map,"out_READ_"+toString(i)+"_ACK ","out_PREDICT_"+toString(i)+"_ACK"); 48 vhdl->set_body_component_port_map (list_port_map," in_READ_"+toString(i)+"_ADDRESS "," in_PREDICT_"+toString(i)+"_ADDRESS"); 49 vhdl->set_body_component_port_map (list_port_map,"out_READ_"+toString(i)+"_DATA ","out_PREDICT_"+toString(i)+"_HISTORY"); 50 50 } 51 51 52 52 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 53 53 { 54 vhdl .set_body_component_port_map (list_port_map," in_WRITE_VAL_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+"");55 vhdl .set_body_component_port_map (list_port_map,"out_WRITE_ACK_"+toString(i)+" "," out_BRANCH_COMPLETE_ACK_"+toString(i)+"");56 vhdl .set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+""," in_BRANCH_COMPLETE_ADDRESS_"+toString(i));57 vhdl .set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));54 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_VAL "," in_BRANCH_COMPLETE_"+toString(i)+"_VAL"); 55 vhdl->set_body_component_port_map (list_port_map,"out_WRITE_"+toString(i)+"_ACK "," out_BRANCH_COMPLETE_"+toString(i)+"_ACK"); 56 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_ADDRESS"," in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); 57 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_DATA ","signal_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"); 58 58 } 59 vhdl .set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map);59 vhdl->set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map); 60 60 }; 61 61 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_port.cpp
r15 r42 18 18 19 19 20 void Branch_History_Table::vhdl_port (Vhdl & vhdl)20 void Branch_History_Table::vhdl_port (Vhdl * & vhdl) 21 21 { 22 vhdl.set_port (" in_CLOCK" , IN, 1); 23 vhdl.set_port (" in_NRESET", IN, 1); 24 25 for (uint32_t i=0; i<_param._nb_prediction; i++) 26 { 27 vhdl.set_port(" in_PREDICT_VAL_"+toString(i)+" ", IN, 1); 28 vhdl.set_port("out_PREDICT_ACK_"+toString(i)+" ",OUT, 1); 29 vhdl.set_port(" in_PREDICT_ADDRESS_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 30 vhdl.set_port("out_PREDICT_HISTORY_"+toString(i)+" ",OUT, _param._size_shifter); 31 } 32 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 33 { 34 vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", IN, 1); 35 vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" ",OUT, 1); 36 vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 37 vhdl.set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+" ", IN, _param._size_shifter); 38 vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"", IN, 1); 39 } 22 _interfaces->set_port(vhdl); 40 23 }; 41 24 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_signal.cpp
r3 r42 17 17 namespace branch_history_table { 18 18 19 void Branch_History_Table::vhdl_signal (Vhdl & vhdl)19 void Branch_History_Table::vhdl_signal (Vhdl * & vhdl) 20 20 { 21 21 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 22 vhdl .set_signal ("signal_BRANCH_COMPLETE_HISTORY_"+toString(i), _param._size_shifter);22 vhdl->set_signal ("signal_BRANCH_COMPLETE_"+toString(i)+"_HISTORY", _param._size_shifter); 23 23 }; 24 24 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_transition.cpp
r15 r42 20 20 void Branch_History_Table::vhdl_testbench_transition (void) 21 21 { 22 // In order with file Branch_History_Table_vhdl_testbench_port.cpp 23 #ifndef SYSTEMCASS_SPECIFIC 24 sc_cycle(0); 25 #endif 22 sc_start(0); 26 23 27 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 28 29 for (uint32_t i=0; i<_param._nb_prediction; i++) 30 { 31 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL [i])); 32 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_ACK [i])); 33 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 34 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i])); 35 //_vhdl_testbench->add_output (PORT_READ(out_PREDICT_HISTORY [i])); 36 } 37 38 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 39 { 40 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL [i])); 41 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_WRITE_ACK [i])); 42 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 43 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY [i])); 44 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION[i])); 45 } 46 47 // add_test : 48 // - True : the cycle must be compare with the output of systemC 49 // - False : no test 50 _vhdl_testbench->add_test(true); 51 52 _vhdl_testbench->new_cycle (); // always at the end 24 _interfaces->testbench(); 53 25 }; 54 26 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_type.cpp
r2 r42 18 18 19 19 20 void Branch_History_Table::vhdl_type (Vhdl & vhdl)20 void Branch_History_Table::vhdl_type (Vhdl * & vhdl) 21 21 { 22 22 };
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