Ignore:
Timestamp:
Jul 5, 2007, 5:50:19 PM (17 years ago)
Author:
rosiere
Message:

Modification des classes d'encapsulation des interfaces :

  • gère les signaux à écrire dans le vhdl
  • les traces pour le testbench
  • la génération des vhdl structurelles

-> test sur la Pattern History Table

File:
1 edited

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Unmodified
Added
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  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_transition.cpp

    r2 r42  
    2222    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_transition","Begin");
    2323
    24 #ifndef SYSTEMCASS_SPECIFIC
    25     sc_cycle(0);
    26 #endif   
     24    sc_start(0);
    2725
    28     // In order with file Two_Level_Branch_Predictor_Glue_vhdl_testbench_port.cpp
    29     // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
    30     // (because we have no control on the ordonnancer's policy)
    31 
    32 //     _vhdl_testbench->add_input (PORT_READ( in_NRESET));
    33     for (uint32_t i=0; i<_param._nb_prediction; i++)
    34       {
    35         if (_param._have_bht)
    36           {
    37         _vhdl_testbench->add_input  (PORT_READ( in_PREDICT_BHT_ACK      [i]));
    38         _vhdl_testbench->add_output (PORT_READ(out_PREDICT_BHT_ADDRESS  [i]));
    39           }
    40         if (_param._have_bht and _param._have_pht)
    41         _vhdl_testbench->add_input  (PORT_READ( in_PREDICT_BHT_HISTORY  [i]));
    42         if (_param._have_pht)
    43           {
    44         _vhdl_testbench->add_input  (PORT_READ( in_PREDICT_PHT_ACK      [i]));
    45         _vhdl_testbench->add_output (PORT_READ(out_PREDICT_PHT_ADDRESS  [i]));
    46           }
    47         _vhdl_testbench->add_output (PORT_READ(out_PREDICT_ACK          [i]));
    48         _vhdl_testbench->add_input  (PORT_READ( in_PREDICT_ADDRESS      [i]));
    49       }
    50 
    51     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    52       {
    53         if (_param._have_bht)
    54           {
    55         _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_BHT_ACK      [i]));
    56         _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_BHT_ADDRESS  [i]));
    57           }
    58         if (_param._have_bht and _param._have_pht)
    59         _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_BHT_HISTORY  [i]));
    60         if (_param._have_pht)
    61           {
    62         _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_PHT_ACK      [i]));
    63         _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_PHT_ADDRESS  [i]));
    64           }
    65         _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_ACK          [i]));
    66         _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_ADDRESS      [i]));
    67       }
    68     // add_test :
    69     //  - True  : the cycle must be compare with the output of systemC
    70     //  - False : no test
    71     _vhdl_testbench->add_test(true);
    72 
    73     _vhdl_testbench->new_cycle (); // always at the end
     26    _interfaces->testbench();
    7427
    7528    log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_transition","End");
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