- Timestamp:
- Jul 5, 2007, 5:50:19 PM (17 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h
r41 r42 44 44 PORT_VHDL_NO_TESTBENCH_NO , 45 45 CLOCK_VHDL_YES , 46 CLOCK_VHDL_NO } presence_port_t; 46 CLOCK_VHDL_NO , 47 RESET_VHDL_YES , 48 RESET_VHDL_NO } presence_port_t; 47 49 48 50 class Signal … … 56 58 private : const presence_port_t _presence_port; 57 59 60 private : Signal * _signal ; 61 private : bool _is_allocate ; 62 private : void * _sc_signal ; 63 private : bool _is_map ; 64 private : void * _sc_signal_map; 65 private : type_info_t _type_info ; 66 58 67 #ifdef VHDL_TESTBENCH 59 private : void * _signal ;60 private : type_info_t _type_info ;61 62 68 private : list<string> * _list_value ; 63 69 #endif … … 71 77 public : ~Signal (); 72 78 73 #ifdef VHDL_TESTBENCH 79 public : string get_name (void); 80 public : uint32_t get_size (void); 81 public : Signal * get_signal_link (void); 82 83 public : bool presence_vhdl (void); 84 public : bool presence_testbench (void); 85 86 public : void mapping (Signal * signal); 87 public : void link (Signal * signal); 88 89 #ifdef SYSTEMC 74 90 public :template <typename T> 75 91 T read (void) … … 88 104 switch (_type_info) 89 105 { 90 case BOOL : return (static_cast<sc_in <bool > *>(_s ignal)->read());91 case UINT8_T : return (static_cast<sc_in <uint8_t > *>(_s ignal)->read());92 case UINT16_T : return (static_cast<sc_in <uint16_t> *>(_s ignal)->read());93 case UINT32_T : return (static_cast<sc_in <uint32_t> *>(_s ignal)->read());94 case UINT64_T : return (static_cast<sc_in <uint64_t> *>(_s ignal)->read());106 case BOOL : return (static_cast<sc_in <bool > *>(_sc_signal_map)->read()); 107 case UINT8_T : return (static_cast<sc_in <uint8_t > *>(_sc_signal_map)->read()); 108 case UINT16_T : return (static_cast<sc_in <uint16_t> *>(_sc_signal_map)->read()); 109 case UINT32_T : return (static_cast<sc_in <uint32_t> *>(_sc_signal_map)->read()); 110 case UINT64_T : return (static_cast<sc_in <uint64_t> *>(_sc_signal_map)->read()); 95 111 default : throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.")); 96 112 } … … 102 118 switch (_type_info) 103 119 { 104 case BOOL : return (static_cast<sc_out <bool > *>(_s ignal)->read());105 case UINT8_T : return (static_cast<sc_out <uint8_t > *>(_s ignal)->read());106 case UINT16_T : return (static_cast<sc_out <uint16_t> *>(_s ignal)->read());107 case UINT32_T : return (static_cast<sc_out <uint32_t> *>(_s ignal)->read());108 case UINT64_T : return (static_cast<sc_out <uint64_t> *>(_s ignal)->read());120 case BOOL : return (static_cast<sc_out <bool > *>(_sc_signal_map)->read()); 121 case UINT8_T : return (static_cast<sc_out <uint8_t > *>(_sc_signal_map)->read()); 122 case UINT16_T : return (static_cast<sc_out <uint16_t> *>(_sc_signal_map)->read()); 123 case UINT32_T : return (static_cast<sc_out <uint32_t> *>(_sc_signal_map)->read()); 124 case UINT64_T : return (static_cast<sc_out <uint64_t> *>(_sc_signal_map)->read()); 109 125 default : throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.")); 110 126 } … … 117 133 throw (ErrorMorpheo ("Signal \""+_name+"\" : already allocate.")); 118 134 119 _signal = port; 135 _is_allocate = true; 136 _sc_signal = port; 137 _sc_signal_map = port; 120 138 121 139 if (typeid(T) == typeid(bool )) … … 136 154 _type_info = UNKNOW; 137 155 } 138 139 public : void testbench (void); 140 public : void testbench_body (Vhdl * & vhdl , 141 string counter_name ); 142 public : void testbench_test_ok(Vhdl * & vhdl ); 143 #endif 156 #endif 157 144 158 #ifdef VHDL 145 159 public : void set_port (Vhdl * & vhdl); 146 160 # ifdef VHDL_TESTBENCH 147 public : string get_clock (void); 161 public : Signal * get_clock (void); 162 public : Signal * get_reset (void); 163 public : uint32_t get_reset_cycle (bool active_low); 164 148 165 public : void set_signal (Vhdl * & vhdl); 149 166 public : void get_name_vhdl (list<string> * & list_signal); 167 168 public : void testbench (void); 169 public : void testbench_body (Vhdl * & vhdl , 170 string counter_name , 171 string reset_name ); 172 public : void testbench_test_ok(Vhdl * & vhdl ); 150 173 # endif 151 174 #endif … … 162 185 switch (x) 163 186 { 164 case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_YES : return "Port is in VHDL's model and TestBench's model" ; break; 165 case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_NO : return "Port is in VHDL's model " ; break; 166 case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_YES : return "Port is in TestBench's model" ; break; 167 case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_NO : return "Port is in none model " ; break; 187 case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_YES : return "Port is in VHDL's model and TestBench's model" ; break; 188 case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_NO : return "Port is in VHDL's model " ; break; 189 case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_YES : return "Port is in TestBench's model" ; break; 190 case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_NO : return "Port is in none model " ; break; 191 case morpheo::behavioural::CLOCK_VHDL_YES : return "Clock is in VHDL's model " ; break; 192 case morpheo::behavioural::CLOCK_VHDL_NO : return "Clock is not in VHDL's model " ; break; 193 case morpheo::behavioural::RESET_VHDL_YES : return "Reset is in VHDL's model " ; break; 194 case morpheo::behavioural::RESET_VHDL_NO : return "Reset is not in VHDL's model " ; break; 168 195 default : return ""; break; 169 196 }
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