Changeset 42 for trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_testbench_generate_file.cpp
- Timestamp:
- Jul 5, 2007, 5:50:19 PM (17 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_testbench_generate_file.cpp
r41 r42 19 19 Vhdl * vhdl = new Vhdl(_name+"_Testbench"); 20 20 string counter = "counter"; 21 string clock = this->get_clock(); 21 Signal * clock = this->get_clock(); 22 Signal * reset = this->get_reset(); 23 string clock_name = clock->get_name(); 24 string reset_name = reset->get_name(); 22 25 uint32_t cycle = this->get_cycle(); 23 26 24 vhdl ->set_signal (counter, "natural", "0"); 25 vhdl ->set_signal (clock , 1 , 0); // modif Signal_set_signal 27 vhdl->set_signal (clock_name, 1, 0); 28 vhdl->set_signal (reset_name, 1, 0); 29 vhdl->set_signal (counter, "natural"); 26 30 this->set_signal (vhdl); 27 31 28 32 vhdl->set_body(""); 29 33 vhdl->set_body("------------------------------------------------------"); 30 vhdl->set_body("-- Component ");34 vhdl->set_body("-- Component - Intanciation"); 31 35 vhdl->set_body("------------------------------------------------------"); 32 36 vhdl->set_body(""); … … 54 58 delete list_signal; 55 59 56 vhdl->set_body(""); 57 vhdl->set_body("------------------------------------------------------"); 58 vhdl->set_body("-- Port's affectation"); 59 vhdl->set_body("------------------------------------------------------"); 60 vhdl->set_body(""); 61 string test_name = this->testbench_body(vhdl,counter); 60 string test_name = this->testbench_body(vhdl,counter, reset_name); 62 61 63 62 vhdl->set_body(""); 64 63 vhdl->set_body("------------------------------------------------------"); 65 vhdl->set_body("-- process clock");64 vhdl->set_body("-- reset"); 66 65 vhdl->set_body("------------------------------------------------------"); 67 66 vhdl->set_body(""); 68 vhdl->set_body(clock+" <= not "+clock+" after 50 ns;"); 67 vhdl->set_body("-- if the systemC simulate have multiple reset, we make the last"); 68 vhdl->set_body(reset_name+" <= '1' after 150 ns;"); 69 69 70 vhdl->set_body(""); 70 vhdl->set_body("process ("+clock+")"); 71 vhdl->set_body("------------------------------------------------------"); 72 vhdl->set_body("-- process clock_name"); 73 vhdl->set_body("------------------------------------------------------"); 74 vhdl->set_body(""); 75 vhdl->set_body(clock_name+" <= not "+clock_name+" after 50 ns;"); 76 vhdl->set_body(""); 77 vhdl->set_body("process ("+clock_name+")"); 71 78 vhdl->set_body("begin"); 72 vhdl->set_body("\tif "+clock+"'event and "+clock+" = '1' then"); 73 vhdl->set_body("\t\t"+counter+" <= "+counter+"+1;"); 79 vhdl->set_body("\tif ("+clock_name+"'event and "+clock_name+" = '1') then"); 74 80 vhdl->set_body(""); 75 vhdl->set_body("\t\tassert ("+test_name+" = '1') report \"Test KO\" severity FAILURE;"); 76 vhdl->set_body("\t\tassert not ("+counter+" = "+toString(cycle)+") report \"Test OK\" severity FAILURE;"); 81 vhdl->set_body("\t\tif ("+reset_name+" = '0') then"); 77 82 vhdl->set_body(""); 83 vhdl->set_body("\t\t\t"+counter+" <= "+toString(reset->get_reset_cycle(true))+";"); 84 vhdl->set_body(""); 85 vhdl->set_body("\t\telse"); 86 vhdl->set_body(""); 87 vhdl->set_body("\t\t\t"+counter+" <= "+counter+"+1;"); 88 vhdl->set_body(""); 89 vhdl->set_body("\t\t\tassert not ("+counter+" = "+toString(cycle)+") report \"Test OK\" severity FAILURE;"); 90 vhdl->set_body("\t\t\tassert not ("+test_name+" = '0') report \"Test KO\" severity FAILURE;"); 91 92 #ifdef VHDL_TESTBENCH_ASSERT 93 vhdl->set_body("\t\t\t-- Assert ..."); 94 for (uint32_t cpt=0; cpt<=cycle; cpt++) 95 vhdl->set_body("\t\t\tassert not ("+counter+" = "+toString(cpt)+") report \"===== Test number "+toString(cpt)+" =====\" severity NOTE;"); 96 #endif 97 98 vhdl->set_body(""); 99 vhdl->set_body("\t\tend if;"); 78 100 vhdl->set_body("\tend if;"); 79 101 vhdl->set_body("end process;"); 80 102 81 vhdl->generate_file(); 103 104 vhdl->generate_file(false,true); 82 105 83 106 delete vhdl;
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