Changeset 57 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_body.cpp
- Timestamp:
- Sep 28, 2007, 2:58:08 PM (17 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_body.cpp
r53 r57 20 20 log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_body","Begin"); 21 21 22 uint32_t read_select_limit ; 23 uint32_t read_nb_select1 ; 24 uint32_t read_nb_select2 ; 25 uint32_t write_select_limit; 26 uint32_t write_nb_select1 ; 27 uint32_t write_nb_select2 ; 28 29 read_select_limit = _param->_nb_port_read%_param->_nb_port_read_by_bank; 30 read_nb_select2 = _param->_nb_port_read/_param->_nb_port_read_by_bank; 31 read_nb_select1 = (read_select_limit==0)?0:(read_nb_select2+1); 32 33 write_select_limit= _param->_nb_port_write%_param->_nb_port_write_by_bank; 34 write_nb_select2 = _param->_nb_port_write/_param->_nb_port_write_by_bank; 35 write_nb_select1 = (write_select_limit==0)?0:(write_nb_select2+1); 36 37 vhdl->set_body(""); 38 vhdl->set_body("-----------------------------------"); 39 vhdl->set_body("-- Instance bank "); 40 vhdl->set_body("-----------------------------------"); 41 vhdl->set_body(""); 42 43 for (uint32_t i=0; i<_param->_nb_bank; i++) 44 { 45 vhdl->set_body(_name+"_bank_"+toString(i)+" : "+_name+"_bank"); 46 vhdl->set_body("port map ("); 47 vhdl->set_body("\t in_CLOCK \t=>\tin_CLOCK "); 48 vhdl->set_body("\t, in_NRESET\t=>\tin_NRESET"); 49 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 50 { 51 vhdl->set_body("\t, in_READ_"+toString(j)+"_VAL \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_VAL"); 52 vhdl->set_body("\t,out_READ_"+toString(j)+"_ACK \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ACK"); 53 vhdl->set_body("\t, in_READ_"+toString(j)+"_ADDRESS \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ADDRESS"); 54 vhdl->set_body("\t,out_READ_"+toString(j)+"_DATA \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_DATA"); 55 } 56 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 57 { 58 vhdl->set_body("\t, in_WRITE_"+toString(j)+"_VAL \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_VAL"); 59 vhdl->set_body("\t,out_WRITE_"+toString(j)+"_ACK \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ACK"); 60 vhdl->set_body("\t, in_WRITE_"+toString(j)+"_ADDRESS \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ADDRESS"); 61 vhdl->set_body("\t, in_WRITE_"+toString(j)+"_DATA \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_DATA"); 62 } 63 64 vhdl->set_body(");"); 65 vhdl->set_body(""); 66 } 67 68 vhdl->set_body(""); 69 vhdl->set_body("-----------------------------------"); 70 vhdl->set_body("-- Instance select"); 71 vhdl->set_body("-- (1 select by port)"); 72 vhdl->set_body("-----------------------------------"); 73 vhdl->set_body(""); 74 for (uint32_t i=0; i<_param->_nb_bank; i++) 75 { 76 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 77 { 78 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((j<read_select_limit)?read_nb_select1:read_nb_select2); 79 80 vhdl->set_body(_name+"_read_select_"+toString(i)+"_"+toString(j)+" : "+_name+"_select_"+toString(nb_port)+"_ports"); 81 vhdl->set_body("port map ("); 82 for (uint32_t k=0; k<nb_port; k++) 83 { 84 uint32_t num_port = _param->_nb_port_read_by_bank*k+j; 85 string separator = ((k==0)?" ":","); 86 87 vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+" \t=>\tinternal_READ_"+toString(i)+"_"+toString(num_port)+"_VAL"); 88 vhdl->set_body("\t,out_ACK_"+toString(k)+" \t=>\tinternal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+"_VAL"); 89 } 90 vhdl->set_body(");"); 91 vhdl->set_body(""); 92 } 93 94 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 95 { 96 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); 97 98 vhdl->set_body(_name+"_write_select_"+toString(i)+"_"+toString(j)+" : "+_name+"_select_"+toString(nb_port)+"_ports"); 99 vhdl->set_body("port map ("); 100 for (uint32_t k=0; k<nb_port; k++) 101 { 102 uint32_t num_port = _param->_nb_port_write_by_bank*k+j; 103 string separator = ((k==0)?" ":","); 104 105 vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+" \t=>\tinternal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL"); 106 vhdl->set_body("\t,out_ACK_"+toString(k)+" \t=>\tinternal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL"); 107 } 108 vhdl->set_body(");"); 109 vhdl->set_body(""); 110 } 111 } 112 113 vhdl->set_body(""); 114 vhdl->set_body("-----------------------------------"); 115 vhdl->set_body("-- Bank Val"); 116 vhdl->set_body("-----------------------------------"); 117 vhdl->set_body(""); 118 for (uint32_t i=0; i<_param->_nb_bank; i++) 119 { 120 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 121 { 122 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((j<read_select_limit)?read_nb_select1:read_nb_select2); 123 124 vhdl->set_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_VAL <= '0'"); 125 for (uint32_t k=0; k<nb_port; k++) 126 { 127 uint32_t num_port = _param->_nb_port_read_by_bank*k+j; 128 129 vhdl->set_body("\tor internal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+"_VAL"); 130 } 131 vhdl->set_body(";"); 132 } 133 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 134 { 135 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); 136 137 vhdl->set_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_VAL <= '0'"); 138 for (uint32_t k=0; k<nb_port; k++) 139 { 140 uint32_t num_port = _param->_nb_port_write_by_bank*k+j; 141 142 vhdl->set_body("\tor internal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL"); 143 } 144 vhdl->set_body(";"); 145 } 146 } 147 148 vhdl->set_body(""); 149 vhdl->set_body("-----------------------------------"); 150 vhdl->set_body("-- Bank Address"); 151 vhdl->set_body("-----------------------------------"); 152 vhdl->set_body(""); 153 for (uint32_t i=0; i<_param->_nb_bank; i++) 154 { 155 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 156 { 157 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((j<read_select_limit)?read_nb_select1:read_nb_select2); 158 159 vhdl->set_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_ADDRESS <="); 160 for (uint32_t k=1; k<nb_port; k++) 161 { 162 uint32_t num_port = _param->_nb_port_read_by_bank*k+j; 163 164 vhdl->set_body("\tin_READ_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+" when internal_READ_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else"); 165 } 166 vhdl->set_body("\tin_READ_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+";"); 167 // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); 168 } 169 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 170 { 171 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); 172 173 vhdl->set_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_ADDRESS <="); 174 for (uint32_t k=1; k<nb_port; k++) 175 { 176 uint32_t num_port = _param->_nb_port_write_by_bank*k+j; 177 178 vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+" when internal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else"); 179 } 180 vhdl->set_body("\tin_WRITE_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+";"); 181 // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); 182 } 183 } 184 185 vhdl->set_body(""); 186 vhdl->set_body("-----------------------------------"); 187 vhdl->set_body("-- Bank Data"); 188 vhdl->set_body("-----------------------------------"); 189 vhdl->set_body(""); 190 for (uint32_t i=0; i<_param->_nb_bank; i++) 191 { 192 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 193 { 194 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); 195 196 vhdl->set_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_DATA <="); 197 for (uint32_t k=1; k<nb_port; k++) 198 { 199 uint32_t num_port = _param->_nb_port_write_by_bank*k+j; 200 201 vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_DATA when internal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else"); 202 } 203 vhdl->set_body("\tin_WRITE_"+toString(j)+"_DATA;"); 204 // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); 205 } 206 } 207 208 vhdl->set_body(""); 209 vhdl->set_body("-----------------------------------"); 210 vhdl->set_body("-- VAL (to Select)"); 211 vhdl->set_body("-----------------------------------"); 212 vhdl->set_body(""); 213 214 for (uint32_t i=0; i<_param->_nb_bank; i++) 215 { 216 for (uint32_t j=0; j<_param->_nb_port_read; j ++) 217 { 218 string address = (_param->_nb_bank==1)?"":("and (in_READ_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+")"); 219 220 vhdl->set_body("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL <= '1' when (in_READ_"+toString(j)+"_VAL='1') "+address+"else '0';"); 221 } 222 for (uint32_t j=0; j<_param->_nb_port_write; j ++) 223 { 224 string address = (_param->_nb_bank==1)?"":("and (in_WRITE_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+")"); 225 vhdl->set_body("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL <= '1' when (in_WRITE_"+toString(j)+"_VAL='1') "+address+" else '0';"); 226 } 227 } 228 229 vhdl->set_body(""); 230 vhdl->set_body("-----------------------------------"); 231 vhdl->set_body("-- OUTPUT"); 232 vhdl->set_body("-----------------------------------"); 233 vhdl->set_body(""); 234 235 if (_param->_crossbar == FULL_CROSSBAR) 236 { 237 for (uint32_t i=0; i<_param->_nb_port_read; i ++) 238 { 239 vhdl->set_body("out_READ_"+toString(i)+"_ACK <= "); 240 for (uint32_t j=0; j<_param->_nb_bank; j ++) 241 { 242 for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k ++) 243 { 244 vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_ACK when internal_SELECT_READ_"+toString(j)+"_"+toString(k)+"_VAL = '1' else"); 245 } 246 } 247 vhdl->set_body("\t'0';"); 248 vhdl->set_body("out_READ_"+toString(i)+"_DATA <= "); 249 for (uint32_t j=0; j<_param->_nb_bank; j ++) 250 { 251 for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k ++) 252 { 253 vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_DATA when internal_SELECT_READ_"+toString(j)+"_"+toString(k)+"_VAL = '1' else"); 254 } 255 } 256 vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); 257 } 258 for (uint32_t i=0; i<_param->_nb_port_write; i ++) 259 { 260 vhdl->set_body("out_WRITE_"+toString(i)+"_ACK <= "); 261 for (uint32_t j=0; j<_param->_nb_bank; j ++) 262 { 263 for (uint32_t k=0; k<_param->_nb_port_write_by_bank; k ++) 264 { 265 vhdl->set_body("\tinternal_BANK_WRITE_"+toString(j)+"_"+toString(k)+"_ACK when internal_SELECT_WRITE_"+toString(j)+"_"+toString(k)+"_VAL = '1' else"); 266 } 267 } 268 vhdl->set_body("\t'0';"); 269 } 270 } 271 else 272 { 273 for (uint32_t i=0; i<_param->_nb_port_read; i ++) 274 { 275 uint32_t link = _param->_link_port_read_to_bank_read[i]; 276 277 vhdl->set_body("out_READ_"+toString(i)+"_ACK <= "); 278 for (uint32_t j=0; j<_param->_nb_bank; j ++) 279 { 280 vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(link)+"_ACK when internal_SELECT_READ_"+toString(j)+"_"+toString(link)+"_VAL = '1' else"); 281 } 282 // vhdl->set_body("\tinternal_BANK_READ_"+toString(0)+"_"+toString(link)+"_ACK;"); 283 vhdl->set_body("\t'0';"); 284 285 vhdl->set_body("out_READ_"+toString(i)+"_DATA <= "); 286 for (uint32_t j=1; j<_param->_nb_bank; j ++) 287 { 288 vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(link)+"_DATA when internal_SELECT_READ_"+toString(j)+"_"+toString(i)+"_VAL = '1' else"); 289 } 290 vhdl->set_body("\tinternal_BANK_READ_"+toString(0)+"_"+toString(link)+"_DATA;"); 291 // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); 292 } 293 for (uint32_t i=0; i<_param->_nb_port_write; i ++) 294 { 295 uint32_t link = _param->_link_port_write_to_bank_write[i]; 296 297 vhdl->set_body("out_WRITE_"+toString(i)+"_ACK <= "); 298 for (uint32_t j=0; j<_param->_nb_bank; j ++) 299 { 300 vhdl->set_body("\tinternal_BANK_WRITE_"+toString(j)+"_"+toString(link)+"_ACK when internal_SELECT_WRITE_"+toString(j)+"_"+toString(i)+"_VAL = '1' else"); 301 } 302 // vhdl->set_body("\tinternal_BANK_WRITE_"+toString(0)+"_"+toString(link)+"_ACK;"); 303 vhdl->set_body("\t'0';"); 304 } 305 } 306 22 307 log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_body","End"); 23 308 }; … … 26 311 }; // end namespace registerfile 27 312 }; // end namespace generic 28 29 313 }; // end namespace behavioural 30 314 }; // end namespace morpheo
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