Ignore:
Timestamp:
Sep 28, 2007, 2:58:08 PM (17 years ago)
Author:
rosiere
Message:
  • VHDL - RegisterFile_Multi_Banked (only partial_crossbar)
  • SystemC - modif Component, interface and co -> ajout du type Tusage_T pour instancier un coposant mais ne demander que le VHDL ou le systemC.
  • Séminaire interne
File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-front_end.fig

    r17 r57  
    1 #FIG 3.2  Produced by xfig version 3.2.5-alpha5
     1#FIG 3.2
    22Landscape
    33Center
    … …  
    3636         3330 6930 2610 6930 2610 6480 3330 6480 3330 6930
    37374 1 0 50 -1 -1 10 0.0000 4 105 315 2970 6660 fetch\001
    38 4 1 0 50 -1 -1 10 0.0000 4 120 345 2970 6840 queue\001
     384 1 0 50 -1 -1 10 0.0000 4 105 345 2970 6840 queue\001
    3939-6
    40406 2610 5670 3330 6120
    … …  
    43434 1 0 50 -1 -1 10 0.0000 4 105 450 2970 5850 address\001
    44444 1 0 50 -1 -1 10 0.0000 4 120 585 2970 6030 generator\001
    45 -6
    46 6 1710 6075 2430 6525
    47 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5
    48          2430 6525 1710 6525 1710 6075 2430 6075 2430 6525
    49 4 1 0 50 -1 -1 10 0.0000 4 105 240 2070 6255 inst\001
    50 4 1 0 50 -1 -1 10 0.0000 4 105 360 2070 6435 ROM\001
    5145-6
    52461 3 0 1 0 0 50 -1 20 0.000 1 0.0000 5040 5221 24 24 5040 5221 5064 5217
    … …  
    102962 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
    10397        3 0 1.00 60.00 120.00
    104          2610 5895 1350 5895
     98         2610 5895 2250 5895
    105992 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 1
    106100         2250 5895
    … …  
    1091032 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
    110104        3 0 1.00 60.00 120.00
    111          2070 5895 2070 6075
    112 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
    113         3 0 1.00 60.00 120.00
    114          1350 6705 2610 6705
    115 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
    116         3 0 1.00 60.00 120.00
    117          2070 6525 2070 6705
    118 2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
    119          3510 5490 1530 5490 1530 7110 3510 7110 3510 5490
     105         2250 6705 2610 6705
    1201062 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
    121107        3 0 1.00 60.00 120.00
    … …  
    1271132 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5
    128114         5310 6930 4590 6930 4590 6480 5310 6480 5310 6930
    129 4 2 0 50 -1 -1 10 0.0000 4 150 435 2880 4320 predict\001
     1152 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5
     116         3510 5490 2430 5490 2430 7110 3510 7110 3510 5490
     1174 2 0 50 -1 -1 10 0.0000 4 135 435 2880 4320 predict\001
    1301184 1 0 50 -1 -1 10 0.0000 4 105 315 4005 6660 fetch\001
    1311194 0 0 50 -1 -1 10 0.0000 4 150 825 5085 6435 decod_branch\001
    1321204 1 0 50 -1 -1 10 0.0000 4 105 360 3600 5805 Event\001
    1331214 1 0 50 -1 -1 10 0.0000 4 105 345 4950 4995 Table\001
    134 4 1 0 50 -1 -1 10 0.0000 4 150 450 4950 4815 Update\001
     1224 1 0 50 -1 -1 10 0.0000 4 135 450 4950 4815 Update\001
    1351234 1 0 50 -1 -1 10 0.0000 4 105 420 4950 4635 Branch\001
    1361244 2 0 50 -1 -1 10 0.0000 4 150 690 4815 6435 decod_sync\001
    137 4 2 0 50 -1 -1 10 0.0000 4 150 405 6705 5715 update\001
     1254 2 0 50 -1 -1 10 0.0000 4 135 405 6705 5715 update\001
    1381264 0 0 50 -1 -1 10 0.0000 4 105 315 3060 6345 alloc\001
    139 4 0 0 50 -1 -1 10 0.0000 4 150 645 1395 5805 Icache_req\001
    140 4 0 0 50 -1 -1 10 0.0000 4 150 645 1395 6885 Icache_rsp\001
    1411274 2 0 50 -1 -1 10 0.0000 4 105 345 6750 7065 decod\001
    1421284 1 0 50 -1 -1 10 0.0000 4 105 345 4950 6750 decod\001
    1431294 1 0 50 -1 -1 10 0.0000 4 105 345 6030 6660 decod\001
    144 4 1 0 50 -1 -1 10 0.0000 4 120 345 6030 6840 queue\001
     1304 1 0 50 -1 -1 10 0.0000 4 105 345 6030 6840 queue\001
     1314 2 0 50 -1 -1 10 0.0000 4 150 645 2340 5805 Icache_req\001
     1324 2 0 50 -1 -1 10 0.0000 4 150 645 2340 6885 Icache_rsp\001
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