Ignore:
Timestamp:
Dec 12, 2007, 5:02:47 PM (17 years ago)
Author:
rosiere
Message:

Station de reservation : systemC et VHDL ok

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_genMoore.cpp

    r56 r69  
    2626    log_printf(FUNC,Reservation_station,FUNCTION,"Begin");
    2727
    28     // ~~~~~[ Interface "reservation_station_in" ]~~~~~~~~~~~~~~~~~~~~~~~~
     28    // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~
    2929   
    3030    // accept a new instructions when reservation_station is not full
    31     internal_RESERVATION_STATION_IN_ACK = not _queue_control->full();
    32    
    33     PORT_WRITE(out_RESERVATION_STATION_IN_ACK, internal_RESERVATION_STATION_IN_ACK);
     31#ifdef  SYSTEMC_VHDL_COMPATIBILITY
     32    for (internal_INSERT_SLOT=0; (internal_INSERT_SLOT<_param->_size_queue) and (_queue_valid[internal_INSERT_SLOT]==true); internal_INSERT_SLOT++);
     33    internal_INSERT_ACK = (internal_INSERT_SLOT<_param->_size_queue);
     34#else
     35    internal_INSERT_ACK = not _queue_control->full();
     36#endif   
     37    PORT_WRITE(out_INSERT_ACK, internal_INSERT_ACK);
    3438
    35     // ~~~~~[ Interface "reservation_station_out" ]~~~~~~~~~~~~~~~~~~~~~~~
     39    // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~
    3640
    37     for (uint32_t i=0; i<_param->_size_queue; i++)
     41    uint32_t nb_slot_find = 0;
     42    for (uint32_t i=0; (
     43#ifdef  SYSTEMC_VHDL_COMPATIBILITY
     44                        (i<_param->_size_queue)
     45#else
     46                        (i<_queue_control->nb_elt())
     47#endif
     48                        and (nb_slot_find < _param->_nb_inst_retire)
     49
     50                        )
     51                        ; i++)
    3852      {
    39         bool     val   = i <_queue_control->nb_elt();
    40         uint32_t index = (*_queue_control)[i];
    41        
     53        uint32_t index;
     54#ifdef  SYSTEMC_VHDL_COMPATIBILITY
     55        index = i;
     56#else
     57        index = (*_queue_control)[i];
     58#endif
     59        bool     val   =
     60          (
     61#ifdef  SYSTEMC_VHDL_COMPATIBILITY
     62           _queue_valid [i]           and
     63#endif
     64           _queue[index]._data_ra_val and
     65           _queue[index]._data_rb_val and
     66           _queue[index]._data_rc_val);
     67
    4268        if (val == true)
    4369          {
    44             // valid if all data is present
    45             val = (_queue[index]._data_ra_val and
    46                    _queue[index]._data_rb_val and
    47                    _queue[index]._data_rc_val);
     70            internal_RETIRE_SLOT [nb_slot_find] = i;
     71            nb_slot_find ++;
     72          }
     73      }
    4874
    49             PORT_WRITE(out_RESERVATION_STATION_OUT_CONTEXT_ID  [index],_queue[index]._context_id);
    50             PORT_WRITE(out_RESERVATION_STATION_OUT_PACKET_ID   [index],_queue[index]._packet_id);
    51             PORT_WRITE(out_RESERVATION_STATION_OUT_OPERATION   [index],_queue[index]._operation);
    52             PORT_WRITE(out_RESERVATION_STATION_OUT_TYPE        [index],_queue[index]._type);
    53             PORT_WRITE(out_RESERVATION_STATION_OUT_HAS_IMMEDIAT[index],_queue[index]._has_immediat);
    54             PORT_WRITE(out_RESERVATION_STATION_OUT_IMMEDIAT    [index],_queue[index]._immediat);
    55             PORT_WRITE(out_RESERVATION_STATION_OUT_DATA_RA     [index],_queue[index]._data_ra);
    56             PORT_WRITE(out_RESERVATION_STATION_OUT_DATA_RB     [index],_queue[index]._data_rb);
    57             PORT_WRITE(out_RESERVATION_STATION_OUT_DATA_RC     [index],_queue[index]._data_rc);
    58             PORT_WRITE(out_RESERVATION_STATION_OUT_WRITE_RD    [index],_queue[index]._write_rd);
    59             PORT_WRITE(out_RESERVATION_STATION_OUT_NUM_REG_RD  [index],_queue[index]._num_reg_rd);
    60             PORT_WRITE(out_RESERVATION_STATION_OUT_WRITE_RE    [index],_queue[index]._write_re);
    61             PORT_WRITE(out_RESERVATION_STATION_OUT_NUM_REG_RE  [index],_queue[index]._num_reg_re);
     75    for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
     76      {
     77        bool val                = i<nb_slot_find;
     78        internal_RETIRE_VAL [i] = val;
     79
     80        PORT_WRITE(out_RETIRE_VAL [i], val);
     81
     82        if (val)
     83          {
     84            uint32_t index;
     85#ifdef  SYSTEMC_VHDL_COMPATIBILITY
     86            index = internal_RETIRE_SLOT [i];
     87#else
     88            index = (*_queue_control)[internal_RETIRE_SLOT [i]];
     89#endif
     90            if (_param->_have_port_context_id)
     91            PORT_WRITE(out_RETIRE_CONTEXT_ID    [i],_queue[index]._context_id);
     92            if (_param->_have_port_front_end_id)
     93            PORT_WRITE(out_RETIRE_FRONT_END_ID  [i],_queue[index]._front_end_id);
     94            if (_param->_have_port_ooo_engine_id)
     95            PORT_WRITE(out_RETIRE_OOO_ENGINE_ID [i],_queue[index]._ooo_engine_id);
     96            if (_param->_have_port_rob_id)
     97            PORT_WRITE(out_RETIRE_ROB_ID        [i],_queue[index]._rob_id);
     98            PORT_WRITE(out_RETIRE_OPERATION     [i],_queue[index]._operation);
     99            PORT_WRITE(out_RETIRE_TYPE          [i],_queue[index]._type);
     100            PORT_WRITE(out_RETIRE_HAS_IMMEDIAT  [i],_queue[index]._has_immediat);
     101            PORT_WRITE(out_RETIRE_IMMEDIAT      [i],_queue[index]._immediat);
     102            PORT_WRITE(out_RETIRE_DATA_RA       [i],_queue[index]._data_ra);
     103            PORT_WRITE(out_RETIRE_DATA_RB       [i],_queue[index]._data_rb);
     104            PORT_WRITE(out_RETIRE_DATA_RC       [i],_queue[index]._data_rc);
     105            PORT_WRITE(out_RETIRE_WRITE_RD      [i],_queue[index]._write_rd);
     106            PORT_WRITE(out_RETIRE_NUM_REG_RD    [i],_queue[index]._num_reg_rd);
     107            PORT_WRITE(out_RETIRE_WRITE_RE      [i],_queue[index]._write_re);
     108            PORT_WRITE(out_RETIRE_NUM_REG_RE    [i],_queue[index]._num_reg_re);
    62109          }
    63        
    64         internal_RESERVATION_STATION_OUT_VAL [index] = val;
    65         PORT_WRITE(out_RESERVATION_STATION_OUT_VAL [index], internal_RESERVATION_STATION_OUT_VAL [index]);
    66110      }
    67111
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