Changeset 78 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
- Timestamp:
- Mar 27, 2008, 11:04:49 AM (16 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r76 r78 5 5 * $Id$ 6 6 * 7 * [ 7 * [ Description ] 8 8 * 9 9 * Ce composant peut être amélioré en placant deux ptr de lecture au lieu d'un : un pour l'accès au cache et un pour le commit … … 46 46 #endif 47 47 { 48 // -----[ 48 // -----[ fields ]---------------------------------------------------- 49 49 // Parameters 50 50 protected : const std::string _name; … … 53 53 54 54 #ifdef STATISTICS 55 p rivate: Stat * _stat;55 public : Stat * _stat; 56 56 57 57 private : counter_t * _stat_use_store_queue; … … 83 83 84 84 #ifdef SYSTEMC 85 // ~~~~~[ 85 // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 86 86 // Interface 87 87 public : SC_CLOCK * in_CLOCK ; 88 88 public : SC_IN (Tcontrol_t) * in_NRESET ; 89 89 90 // ~~~~~[ 90 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 91 91 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_VAL ; 92 92 public : SC_OUT(Tcontrol_t ) * out_MEMORY_IN_ACK ; … … 96 96 public : SC_IN (Tpacket_t ) * in_MEMORY_IN_PACKET_ID ; 97 97 public : SC_IN (Toperation_t ) * in_MEMORY_IN_OPERATION ; 98 //public : SC_IN (Ttype_t ) * in_MEMORY_IN_TYPE ;98 public : SC_IN (Ttype_t ) * in_MEMORY_IN_TYPE ; 99 99 public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 100 100 public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; 101 //public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_HAS_IMMEDIAT;101 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_HAS_IMMEDIAT; 102 102 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_IMMEDIAT ; // memory address 103 103 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RA ; // memory address 104 104 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RB ; // data (store) 105 //public : SC_IN (Tspecial_data_t ) * in_MEMORY_IN_DATA_RC ;106 //public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RD ; // = (operation==load)105 public : SC_IN (Tspecial_data_t ) * in_MEMORY_IN_DATA_RC ; 106 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RD ; // = (operation==load) 107 107 public : SC_IN (Tgeneral_address_t) * in_MEMORY_IN_NUM_REG_RD ; // destination (load) 108 //public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RE ;109 //public : SC_IN (Tspecial_address_t) * in_MEMORY_IN_NUM_REG_RE ;110 111 // ~~~~~[ 108 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RE ; 109 public : SC_IN (Tspecial_address_t) * in_MEMORY_IN_NUM_REG_RE ; 110 111 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 112 112 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_VAL ; 113 113 public : SC_IN (Tcontrol_t ) * in_MEMORY_OUT_ACK ; … … 116 116 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_OOO_ENGINE_ID; 117 117 public : SC_OUT(Tpacket_t ) * out_MEMORY_OUT_PACKET_ID ; 118 //public : SC_OUT(Toperation_t ) * out_MEMORY_OUT_OPERATION ; 119 public : SC_OUT(Ttype_t ) * out_MEMORY_OUT_TYPE ; 118 120 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RD ; // = (operation==load) 119 121 public : SC_OUT(Tgeneral_address_t) * out_MEMORY_OUT_NUM_REG_RD; // destination (load) 120 122 public : SC_OUT(Tgeneral_data_t ) * out_MEMORY_OUT_DATA_RD ; // data (load) 121 //public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RE ;122 //public : SC_OUT(Tspecial_address_t) * out_MEMORY_OUT_NUM_REG_RE;123 //public : SC_OUT(Tspecial_data_t ) * out_MEMORY_OUT_DATA_RE ;123 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RE ; 124 public : SC_OUT(Tspecial_address_t) * out_MEMORY_OUT_NUM_REG_RE; 125 public : SC_OUT(Tspecial_data_t ) * out_MEMORY_OUT_DATA_RE ; 124 126 public : SC_OUT(Texception_t ) * out_MEMORY_OUT_EXCEPTION ; 125 126 // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 127 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_NO_SEQUENCE; 128 public : SC_OUT(Tgeneral_data_t ) * out_MEMORY_OUT_ADDRESS ; 129 130 131 // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 127 132 public : SC_OUT(Tcontrol_t ) * out_DCACHE_REQ_VAL ; 128 133 public : SC_IN (Tcontrol_t ) * in_DCACHE_REQ_ACK ; … … 133 138 public : SC_OUT(Tdcache_data_t ) * out_DCACHE_REQ_WDATA ; 134 139 135 // ~~~~~[ Interface "dcache_rsp"]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~140 // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 136 141 public : SC_IN (Tcontrol_t ) * in_DCACHE_RSP_VAL ; 137 142 public : SC_OUT(Tcontrol_t ) * out_DCACHE_RSP_ACK ; … … 141 146 public : SC_IN (Tdcache_error_t ) * in_DCACHE_RSP_ERROR ; 142 147 143 // ~~~~~[ 148 // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 144 149 public : SC_OUT(Tcontrol_t ) ** out_BYPASS_MEMORY_VAL ; 145 150 public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_OOO_ENGINE_ID; … … 147 152 public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_MEMORY_DATA ; 148 153 149 // ~~~~~[ 154 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 150 155 protected : Tstore_queue_entry_t * _store_queue; 151 156 protected : Tload_queue_entry_t * _load_queue; … … 160 165 public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_retire) (void); 161 166 162 // ~~~~~[ 163 164 // ~~~~~[ 167 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 168 169 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 165 170 166 171 // Registers … … 182 187 #endif 183 188 184 // -----[ 189 // -----[ methods ]--------------------------------------------------- 185 190 186 191 #ifdef SYSTEMC
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