Ignore:
Timestamp:
Mar 27, 2008, 11:04:49 AM (16 years ago)
Author:
rosiere
Message:

Add :

  • Execute_loop (must be test systemC)
  • Prediction
    • Direction : predifined scheme
    • Branch Target Buffer
  • iFetch_unit
    • ifetch_queue
    • pc management
  • Decod_unit
    • coming soon : support for custom operation
  • Rename_unit
    • RAT
    • Free_list
    • Dependence RAW check
    • Load store unit pointer
  • New Environnement (hierarchy_memory will remove in a next version)


Modif :

  • Manage Custom Operation
  • All component in execute_loop to use the new statistics management

Not Finish :

  • Return Address Stack
  • Environnement
File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp

    r75 r78  
    7272   in_MEMORY_IN_PACKET_ID             = interface->set_signal_in  <Tpacket_t         > ("packet_id"    ,_param->_size_packet_id       );
    7373   in_MEMORY_IN_OPERATION             = interface->set_signal_in  <Toperation_t      > ("operation"   ,_param->_size_operation        );
     74   in_MEMORY_IN_TYPE                  = interface->set_signal_in  <Ttype_t           > ("type"        ,_param->_size_type             );
    7475   in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in  <Tlsq_ptr_t        > ("store_queue_ptr_write" ,_param->_size_address_store_queue+1); // +1 cf load_queue usage
     76   if (_param->_have_port_load_queue_ptr)
    7577   in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = interface->set_signal_in  <Tlsq_ptr_t        > ("load_queue_ptr_write"  ,_param->_size_address_load_queue );
    76 // in_MEMORY_IN_HAS_IMMEDIAT          = interface->set_signal_in  <Tcontrol_t        > ("has_immediat",1                              );
     78  in_MEMORY_IN_HAS_IMMEDIAT          = interface->set_signal_in  <Tcontrol_t        > ("has_immediat",1                              );
    7779   in_MEMORY_IN_IMMEDIAT              = interface->set_signal_in  <Tgeneral_data_t   > ("immediat"    ,_param->_size_general_data     );
    7880   in_MEMORY_IN_DATA_RA               = interface->set_signal_in  <Tgeneral_data_t   > ("data_ra"     ,_param->_size_general_data     );
    7981   in_MEMORY_IN_DATA_RB               = interface->set_signal_in  <Tgeneral_data_t   > ("data_rb"     ,_param->_size_general_data     );
    80 // in_MEMORY_IN_DATA_RC               = interface->set_signal_in  <Tspecial_data_t   > ("data_rc"     ,_param->_size_special_data     );
    81 //    in_MEMORY_IN_WRITE_RD              = interface->set_signal_in  <Tcontrol_t        > ("write_rd"    ,1                              );
     82  in_MEMORY_IN_DATA_RC               = interface->set_signal_in  <Tspecial_data_t   > ("data_rc"     ,_param->_size_special_data     );
     83   in_MEMORY_IN_WRITE_RD              = interface->set_signal_in  <Tcontrol_t        > ("write_rd"    ,1                              );
    8284   in_MEMORY_IN_NUM_REG_RD            = interface->set_signal_in  <Tgeneral_address_t> ("num_reg_rd"  ,1                              );
    83 // in_MEMORY_IN_WRITE_RE              = interface->set_signal_in  <Tcontrol_t        > ("write_re"    ,1                              );
    84 // in_MEMORY_IN_NUM_REG_RE            = interface->set_signal_in  <Tspecial_address_t> ("num_reg_re"  ,1                              );
     85  in_MEMORY_IN_WRITE_RE              = interface->set_signal_in  <Tcontrol_t        > ("write_re"    ,1                              );
     86  in_MEMORY_IN_NUM_REG_RE            = interface->set_signal_in  <Tspecial_address_t> ("num_reg_re"  ,1                              );
    8587    }
    8688
    … …  
    105107      if (_param->_have_port_packet_id)       
    106108      out_MEMORY_OUT_PACKET_ID     = interface->set_signal_out <Tpacket_t         > ("packet_id"     ,_param->_size_packet_id        );
     109//    out_MEMORY_OUT_OPERATION     = interface->set_signal_out <Toperation_t      > ("operation"     ,_param->_size_operation        );
     110      out_MEMORY_OUT_TYPE          = interface->set_signal_out <Ttype_t           > ("type"          ,_param->_size_type             );
    107111      out_MEMORY_OUT_WRITE_RD      = interface->set_signal_out <Tcontrol_t        > ("write_rd"      ,1                              );
    108112      out_MEMORY_OUT_NUM_REG_RD    = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd"    ,_param->_size_general_register );
    109113      out_MEMORY_OUT_DATA_RD       = interface->set_signal_out <Tgeneral_data_t   > ("data_rd"       ,_param->_size_general_data     );
    110 //    out_MEMORY_OUT_WRITE_RE      = interface->set_signal_out <Tcontrol_t        > ("write_rd"      ,1                              );
    111 //    out_MEMORY_OUT_NUM_REG_RE    = interface->set_signal_out <Tspecial_address_t> ("num_reg_re"    ,_param->_size_general_register );
    112 //    out_MEMORY_OUT_DATA_RE       = interface->set_signal_out <Tspecial_data_t   > ("data_re"       ,_param->_size_general_data     );
     114      out_MEMORY_OUT_WRITE_RE      = interface->set_signal_out <Tcontrol_t        > ("write_re"      ,1                              );
     115      out_MEMORY_OUT_NUM_REG_RE    = interface->set_signal_out <Tspecial_address_t> ("num_reg_re"    ,_param->_size_general_register );
     116      out_MEMORY_OUT_DATA_RE       = interface->set_signal_out <Tspecial_data_t   > ("data_re"       ,_param->_size_general_data     );
    113117      out_MEMORY_OUT_EXCEPTION     = interface->set_signal_out <Texception_t      > ("exception"     ,_param->_size_exception        );
     118      out_MEMORY_OUT_NO_SEQUENCE   = interface->set_signal_out <Tcontrol_t        > ("no_sequence"   ,1                              );
     119      out_MEMORY_OUT_ADDRESS       = interface->set_signal_out <Tgeneral_data_t   > ("address"       ,_param->_size_general_data     );
    114120    }
    115121
    … …  
    153159    // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    154160
    155     if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
     161//  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
    156162      {
    157         out_BYPASS_MEMORY_VAL          = new SC_OUT(Tcontrol_t        ) * [_param->_size_load_queue];
     163        out_BYPASS_MEMORY_VAL          = new SC_OUT(Tcontrol_t        ) * [_param->_nb_bypass_memory];
    158164        if (_param->_have_port_ooo_engine_id)   
    159         out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t        ) * [_param->_size_load_queue];
    160         out_BYPASS_MEMORY_NUM_REG      = new SC_OUT(Tgeneral_address_t) * [_param->_size_load_queue];
    161         out_BYPASS_MEMORY_DATA         = new SC_OUT(Tgeneral_data_t   ) * [_param->_size_load_queue];
     165        out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t        ) * [_param->_nb_bypass_memory];
     166        out_BYPASS_MEMORY_NUM_REG      = new SC_OUT(Tgeneral_address_t) * [_param->_nb_bypass_memory];
     167        out_BYPASS_MEMORY_DATA         = new SC_OUT(Tgeneral_data_t   ) * [_param->_nb_bypass_memory];
    162168       
    163         for (uint32_t i=0; i<_param->_size_load_queue; i++)
     169        for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
    164170          {
    165171            Interface_fifo * interface = _interfaces->set_interface("memory_out"
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