Changeset 78 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp

Timestamp:

Mar 27, 2008, 11:04:49 AM (16 years ago)

Author:

rosiere

Message:

Add :

• Execute_loop (must be test systemC)
• Prediction
  • Direction : predifined scheme
  • Branch Target Buffer
• iFetch_unit
  • ifetch_queue
  • pc management
• Decod_unit
  • coming soon : support for custom operation
• Rename_unit
  • RAT
  • Free_list
  • Dependence RAW check
  • Load store unit pointer
• New Environnement (hierarchy_memory will remove in a next version)

Modif :

• Manage Custom Operation
• All component in execute_loop to use the new statistics management

Not Finish :

• Return Address Stack
• Environnement

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (modified) (2 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp

@@ -120 +120 @@
     if (_param->_have_port_packet_id)
     PORT_WRITE(out_MEMORY_OUT_PACKET_ID    , memory_out_packet_id    );
+//  PORT_WRITE(out_MEMORY_OUT_OPERATION    , memory_out_operation    );
+    PORT_WRITE(out_MEMORY_OUT_TYPE         , TYPE_MEMORY             );
     PORT_WRITE(out_MEMORY_OUT_WRITE_RD     , memory_out_write_rd     );
     PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   , memory_out_num_reg_rd   );
@@ -126 +128 @@
 //  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   , memory_out_num_reg_re   );
 //  PORT_WRITE(out_MEMORY_OUT_DATA_RE      , memory_out_data_re      );
+    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     , 0);
+    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   , 0);
+    PORT_WRITE(out_MEMORY_OUT_DATA_RE      , 0);
     PORT_WRITE(out_MEMORY_OUT_EXCEPTION    , memory_out_exception    );
-
+    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  , 0);
+    PORT_WRITE(out_MEMORY_OUT_ADDRESS      , 0);
     // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~