Changeset 81 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
- Timestamp:
- Apr 15, 2008, 8:40:01 PM (16 years ago)
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- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
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r78 r81 24 24 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); 25 25 26 if (PORT_READ(in_NRESET) == 0) 27 { 28 for (uint32_t i=0; i<_param->_nb_context; i++) 29 { 30 reg_TOP [i] = 0; 31 reg_BOTTOM [i] = 0; 32 reg_NB_ELT [i] = 0; 33 reg_NB_ELT_NEED_UPDATE [i] = 0; 34 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 35 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY; 36 } 37 reg_UPDATE_PRIORITY = 0; 38 } 39 else 40 { 41 // =================================================================== 42 // =====[ PREDICT ]=================================================== 43 // =================================================================== 44 for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 45 if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i]) 46 { 47 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; 48 uint32_t top = reg_TOP [context]; 49 50 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"PREDICT[%d] - Accepted",i); 51 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 52 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 53 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * nb_elt : %d",reg_NB_ELT[context]); 54 55 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_WAIT_DECOD; 56 reg_UPDATE_PREDICTION_TABLE [context][top]._ifetch_prediction = true; 57 reg_UPDATE_PREDICTION_TABLE [context][top]._condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); 58 reg_UPDATE_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); 59 reg_UPDATE_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); 60 reg_UPDATE_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]); 61 //reg_UPDATE_PREDICTION_TABLE [context][top]._good_take 62 reg_UPDATE_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0; 63 reg_UPDATE_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]); 64 reg_UPDATE_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]); 65 66 reg_TOP [context] = (top+1)%_param->_size_queue [context]; 67 reg_NB_ELT [context] ++; 68 } 69 70 // =================================================================== 71 // =====[ DECOD ]===================================================== 72 // =================================================================== 73 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 74 if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i]) 75 { 76 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; 77 Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); 78 79 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"DECOD[%d] - Accepted",i); 80 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 81 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 82 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * nb_elt : %d",reg_NB_ELT[context]); 83 84 // Test if miss ifetch 85 // miss ifetch = decod a branch and the predict unit have not predict this branch ... gloup :P 86 if (miss) 87 { 88 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0; 89 Tdepth_t top = reg_TOP [context]; 90 91 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_WAITEND; 92 reg_UPDATE_PREDICTION_TABLE [context][top]._ifetch_prediction = false; // static prediction 93 reg_UPDATE_PREDICTION_TABLE [context][top]._condition = PORT_READ(in_DECOD_BTB_CONDITION [i]); 94 reg_UPDATE_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]); 95 reg_UPDATE_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]); 96 reg_UPDATE_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]); 97 //reg_UPDATE_PREDICTION_TABLE [context][top]._good_take 98 //reg_UPDATE_PREDICTION_TABLE [context][top]._history 99 reg_UPDATE_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]); 100 reg_UPDATE_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]); 101 102 // Invalid all previous "ifetch" prediction 103 // (ifetch prediction = prediction make in fetch stage and not again comming in decod stage) 104 uint32_t nb_elt_miss = ((top> depth)?top:(top+_param->_size_queue[context]))-depth; 105 uint32_t nb_elt_need_update = 0; 106 for (uint32_t j=0; j<nb_elt_miss; j++) 107 { 108 uint32_t k=(depth+j)%_param->_size_queue[context]; 109 110 // Ifetch have make a prediction and it's a miss 111 // When ifetch predict : 112 // * btb is not change -> needn't update 113 // * direction is not change -> needn't update 114 // * ras have change -> need update 115 116 Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][k]._condition; 117 if ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or 118 (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or 119 (cond == BRANCH_CONDITION_READ_STACK)) 120 { 121 nb_elt_need_update ++; 122 reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_KO; 123 } 124 else 125 { 126 reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_END; 127 } 128 } 129 130 reg_TOP [context] = (depth+1)%_param->_size_queue [context]; 131 reg_NB_ELT_NEED_UPDATE [context] += nb_elt_need_update; 132 reg_NB_ELT [context] ++; 133 } 134 else 135 { 136 // Normal case : branch is previous predicated, change state of branch 137 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0; 138 139 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_WAITEND; 140 } 141 } 142 143 // =================================================================== 144 // =====[ BRANCH_COMPLETE ]=========================================== 145 // =================================================================== 146 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 147 if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i]) 148 { 149 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 150 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 151 152 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"BRANCH_COMPLETE[%d] - Accepted",i); 153 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 154 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 155 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * nb_elt : %d",reg_NB_ELT[context]); 156 157 if (internal_BRANCH_COMPLETE_MISS_PREDICTION [i]) 158 { 159 // Miss case 160 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; 161 162 // Another prediction (prediction with depth higer) 163 Tdepth_t top = reg_TOP [context]; 164 uint32_t nb_elt_miss = ((top> depth)?top:(top+_param->_size_queue[context]))-depth; 165 uint32_t nb_elt_need_update = 1; 166 for (uint32_t j=1; j<nb_elt_miss; j++) 167 { 168 uint32_t k=(depth+j)%_param->_size_queue[context]; 169 170 // Ifetch have make a prediction and it's a miss 171 // When ifetch predict : 172 // * btb is not change -> needn't update 173 // * direction is not change -> needn't update 174 // * ras have change -> need update 175 176 Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][k]._condition; 177 if ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or 178 (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or 179 (cond == BRANCH_CONDITION_READ_STACK)) 180 { 181 nb_elt_need_update ++; 182 reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_KO; 183 } 184 else 185 { 186 reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_END; 187 } 188 } 189 reg_NB_ELT_NEED_UPDATE [context] += nb_elt_need_update; 190 191 // Update pointer : 192 reg_TOP [context] = depth; 193 reg_NB_ELT [context] -= nb_elt_miss; 194 } 195 else 196 { 197 // Hit case 198 #ifdef DEBUG_TEST 199 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAITEND) 200 ERRORMORPHEO(FUNCTION,"Branche complete : invalid state"); 201 #endif 202 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK; 203 } 204 205 // In all case : update good_take and address_destination 206 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = internal_BRANCH_COMPLETE_TAKE [i]; 207 reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; 208 } 209 210 // =================================================================== 211 // =====[ UPDATE ]==================================================== 212 // =================================================================== 213 for (uint32_t i=0; i<_param->_nb_inst_update; i++) 214 if (internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) 215 { 216 Tcontext_t context = internal_UPDATE_CONTEXT_ID [i]; 217 Tdepth_t depth = internal_UPDATE_DEPTH [i]; 218 219 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"UPDATE[%d] - Accepted",i); 220 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 221 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 222 223 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) 224 reg_NB_ELT_NEED_UPDATE [context] --; 225 226 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END; 227 } 228 229 // Round robin 230 reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; 231 232 // =================================================================== 233 // =====[ GARBAGE COLLECTOR ]========================================= 234 // =================================================================== 235 236 for (uint32_t i=0; i<_param->_nb_context; i++) 237 { 238 uint32_t bottom = reg_BOTTOM [i]; 239 240 // Test if the tail of queue is finish (ok or ko and update) 241 if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END) 242 { 243 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"GARBAGE_COLLECTOR"); 244 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i); 245 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",bottom); 246 247 reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY; 248 reg_BOTTOM [i] = (bottom+1)%_param->_size_queue [i]; 249 if (reg_NB_ELT [i]>0) 250 reg_NB_ELT [i] --; 251 } 252 } 253 } 254 255 // #if (DEBUG >= DEBUG_TRACE) 256 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"Dump Update_Prediction_Table"); 257 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY); 258 for (uint32_t i=0; i<_param->_nb_context; i++) 259 { 260 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i); 261 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_TOP : %d",reg_TOP [i]); 262 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_BOTTOM : %d",reg_BOTTOM [i]); 263 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_NB_ELT : %d",reg_NB_ELT [i]); 264 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_NB_ELT_NEED_UPDATE : %d",reg_NB_ELT_NEED_UPDATE [i]); 265 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 266 log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %s %x",j,toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str(),reg_UPDATE_PREDICTION_TABLE [i][j]._address_src); 267 } 268 // #endif 269 270 26 271 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 27 272 end_cycle (); -
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