Changeset 81 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags

Timestamp:

Apr 15, 2008, 8:40:01 PM (17 years ago)

Author:

rosiere

Message:

• Finish Environment (and test)
• Continue predictor_unit
• Add external tools
• svn keyword "Id" set

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags (modified) (1 diff, 1 prop)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags

@@ -18 +18 @@
                                         -DSTATISTICS            \
                                         -DDEBUG=DEBUG_TRACE
-#
-#
+
 #                                       -DVHDL                  \
 #                                       -DVHDL_TESTBENCH        \
 #                                       -DVHDL_TESTBENCH_ASSERT \
-#                                       -DCONFIGURATION         \
 #                                       -DPOSITION              \
+#                                       -DNO_TRANSLATE          \
 
 # Flags :
-# DEBUG={level}                        - Print Debug Message
-# SYSTEMC                              - To generate a systemc's model
-# VHDL                                 - To generate a vhdl's    models
-# VHDL_TESTBENCH        (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model
-# VHDL_TESTBENCH_ASSERT (need SYSTEMC) - In the simulation, generate in  testbench's file an serie of assert
-# STATISTICS            (need SYSTEMC) - In the simulation, generate a statistics's file
-# POSITION                             - To generate a position's files     (it's input of viewer)
-# CONFIGURATION                        - To generate a configuration's file (it's input of viewer and generator)
-# NO_TRANSLATE                         - No translate message
+# DEBUG={level}                           - Print Debug Message
+# SYSTEMC                                 - To generate a systemc's model
+# VHDL                                    - To generate a vhdl's    models
+# VHDL_TESTBENCH        (need SYSTEMC)    - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model
+# VHDL_TESTBENCH_ASSERT (need SYSTEMC)    - In the simulation, generate in  testbench's file an serie of assert
+# POSITION                                - To generate a position's files     (it's input of viewer)
+# STATISTICS            (need SYSTEMC)    - In the simulation, generate a statistics's file
+# INFORMATION           (need STATISTICS) - Instance Information :
+#                                             * Static    : at the instance creation
+#                                                * register number
+#                                                * worst way
+#                                             * Dynamique : at the runtime
+#                                                * consomation
+# NO_TRANSLATE                            - No translate message
+# NO_INIT                                 - No init a lot of register