Changeset 85 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src

Timestamp:

May 14, 2008, 3:09:48 PM (16 years ago)

Author:

rosiere

Message:

• Ifetch_unit : systemC test ok
• modif shell script and makefile.tools : SHELL=/bin/bash

Location:

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src

Files:

• Ifetch_unit_Glue.cpp (modified) (2 diffs)
• Ifetch_unit_Glue_allocation.cpp (modified) (1 diff)
• Ifetch_unit_Glue_deallocation.cpp (modified) (1 diff)
• Ifetch_unit_Glue_genMealy_icache_req.cpp (modified) (1 diff)
• Parameters.cpp (modified) (1 diff)
• Parameters_print.cpp (modified) (1 diff)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue.cpp

@@ -88 +88 @@
         sensitive << (*(in_ICACHE_REQ_ADDRESS_VAL))
                   << (*(in_ICACHE_REQ_ACK        ))
-                  << (*(in_ICACHE_REQ_QUEUE_ACK  ));
+                  << (*(in_ICACHE_REQ_QUEUE_ACK  ))
+                  << (*(in_ICACHE_REQ_ADDRESS_ADDRESS))
+          ;
         
 # ifdef SYSTEMCASS_SPECIFIC
@@ -100 +102 @@
         (*(out_ICACHE_REQ_ADDRESS_ACK)) (*( in_ICACHE_REQ_QUEUE_ACK  ));
         (*(out_ICACHE_REQ_ADDRESS_ACK)) (*( in_ICACHE_REQ_ACK        ));
+
+        (*(out_ICACHE_REQ_ADDRESS      )) (*( in_ICACHE_REQ_ADDRESS_ADDRESS));
+        (*(out_ICACHE_REQ_QUEUE_ADDRESS)) (*( in_ICACHE_REQ_ADDRESS_ADDRESS));
+
 # endif    
 

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp

@@ -60 +60 @@
       ALLOC_INTERFACE("icache_req",OUT, WEST, "Instruction Cache request.");
 
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_VAL        ,"val"        ,Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_VAL,"address_val",Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_VAL  ,"queue_val"  ,Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ACK        ,"ack"        ,Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS_ACK,"address_ack",Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK  ,"queue_ack"  ,Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE       ,"type"       ,Ticache_type_t,_param->_size_icache_type);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_VAL            ,"val"            ,Tcontrol_t,1);
+      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_VAL    ,"address_val"    ,Tcontrol_t,1);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_VAL      ,"queue_val"      ,Tcontrol_t,1);
+      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ACK            ,"ack"            ,Tcontrol_t,1);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS_ACK    ,"address_ack"    ,Tcontrol_t,1);
+      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK      ,"queue_ack"      ,Tcontrol_t,1);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE           ,"type"           ,Ticache_type_t,_param->_size_icache_type);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS        ,"address"        ,Taddress_t,_param->_size_address);
+      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_ADDRESS,"address_address",Taddress_t,_param->_size_address);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_ADDRESS  ,"queue_address"  ,Taddress_t,_param->_size_address);
     }
 

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp

@@ -35 +35 @@
         delete     in_ICACHE_REQ_QUEUE_ACK   ;
         delete    out_ICACHE_REQ_TYPE        ;
+        delete    out_ICACHE_REQ_ADDRESS         ;
+        delete     in_ICACHE_REQ_ADDRESS_ADDRESS ;
+        delete    out_ICACHE_REQ_QUEUE_ADDRESS   ;
         
         delete     in_EVENT_VAL              ;

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_genMealy_icache_req.cpp

@@ -31 +31 @@
     PORT_WRITE(out_ICACHE_REQ_ADDRESS_ACK, ack         and queue_ack); // cache can accept a new transaction and queue have a slot empty
     PORT_WRITE(out_ICACHE_REQ_QUEUE_VAL  , address_val and ack); // cache can accept a new transaction and the address is valid
+
+    Taddress_t address     = PORT_READ(in_ICACHE_REQ_ADDRESS_ADDRESS);
+    PORT_WRITE(out_ICACHE_REQ_ADDRESS      ,address);
+    PORT_WRITE(out_ICACHE_REQ_QUEUE_ADDRESS,address);
     
     log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters.cpp

@@ -19 +19 @@
 #undef  FUNCTION
 #define FUNCTION "Ifetch_unit_Glue::Parameters"
-  Parameters::Parameters ()
+  Parameters::Parameters (uint32_t size_address)
   {
     log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin");
+
+    _size_address = size_address;
+
     test();
     log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters_print.cpp

@@ -27 +27 @@
 
     xml.balise_open("ifetch_unit_glue");
-//  xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end();
+    xml.singleton_begin("size_address"); xml.attribut("value",toString(_size_address)); xml.singleton_end();
     xml.balise_close();