Changeset 88 for trunk/IPs/systemC/Environment/include
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (16 years ago)
- Location:
- trunk/IPs/systemC/Environment/include
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/Environment/include/Cache_Access.h
r81 r88 22 22 }; 23 23 24 Cache_Access ireq_type2cache_type ( Ticache_type_t ireq_type, bool uncached);25 Cache_Access dreq_type2cache_type ( Tdcache_type_t dreq_type, bool uncached);24 Cache_Access ireq_type2cache_type (morpheo::Ticache_type_t ireq_type, bool uncached); 25 Cache_Access dreq_type2cache_type (morpheo::Tdcache_type_t dreq_type, bool uncached); 26 26 }; 27 27 #endif -
trunk/IPs/systemC/Environment/include/Environment.h
r81 r88 20 20 namespace environment { 21 21 22 typedef Respons< Ticache_context_t, Ticache_packet_t,Ticache_error_t> irsp_t;23 typedef Respons< Tdcache_context_t, Tdcache_packet_t,Tdcache_error_t> drsp_t;22 typedef Respons<morpheo::Ticache_context_t, morpheo::Ticache_packet_t,morpheo::Ticache_error_t> irsp_t; 23 typedef Respons<morpheo::Tdcache_context_t, morpheo::Tdcache_packet_t,morpheo::Tdcache_error_t> drsp_t; 24 24 25 25 class Environment : public sc_module … … 29 29 public : sc_in<bool> * NRESET ; 30 30 31 public : sc_in < Tcontrol_t > *** ICACHE_REQ_VAL ;32 public : sc_out< Tcontrol_t > *** ICACHE_REQ_ACK ;33 public : sc_in < Ticache_context_t > *** ICACHE_REQ_CONTEXT_ID ;34 public : sc_in < Ticache_packet_t > *** ICACHE_REQ_PACKET_ID ;35 public : sc_in < Ticache_address_t > *** ICACHE_REQ_ADDRESS ;36 public : sc_in < Ticache_type_t > *** ICACHE_REQ_TYPE ;31 public : sc_in <morpheo::Tcontrol_t > *** ICACHE_REQ_VAL ;//[nb_entity][icache_dedicated_nb_port] 32 public : sc_out<morpheo::Tcontrol_t > *** ICACHE_REQ_ACK ;//[nb_entity][icache_dedicated_nb_port] 33 public : sc_in <morpheo::Ticache_context_t > *** ICACHE_REQ_CONTEXT_ID ;//[nb_entity][icache_dedicated_nb_port] 34 public : sc_in <morpheo::Ticache_packet_t > *** ICACHE_REQ_PACKET_ID ;//[nb_entity][icache_dedicated_nb_port] 35 public : sc_in <morpheo::Ticache_address_t > *** ICACHE_REQ_ADDRESS ;//[nb_entity][icache_dedicated_nb_port] 36 public : sc_in <morpheo::Ticache_type_t > *** ICACHE_REQ_TYPE ;//[nb_entity][icache_dedicated_nb_port] 37 37 38 public : sc_out< Tcontrol_t > *** ICACHE_RSP_VAL ;39 public : sc_in < Tcontrol_t > *** ICACHE_RSP_ACK ;40 public : sc_out< Ticache_context_t > *** ICACHE_RSP_CONTEXT_ID ;41 public : sc_out< Ticache_packet_t > *** ICACHE_RSP_PACKET_ID ;42 public : sc_out< Ticache_instruction_t> **** ICACHE_RSP_INSTRUCTION;//[nb_instruction]43 public : sc_out< Ticache_error_t > *** ICACHE_RSP_ERROR ;38 public : sc_out<morpheo::Tcontrol_t > *** ICACHE_RSP_VAL ;//[nb_entity][icache_dedicated_nb_port] 39 public : sc_in <morpheo::Tcontrol_t > *** ICACHE_RSP_ACK ;//[nb_entity][icache_dedicated_nb_port] 40 public : sc_out<morpheo::Ticache_context_t > *** ICACHE_RSP_CONTEXT_ID ;//[nb_entity][icache_dedicated_nb_port] 41 public : sc_out<morpheo::Ticache_packet_t > *** ICACHE_RSP_PACKET_ID ;//[nb_entity][icache_dedicated_nb_port] 42 public : sc_out<morpheo::Ticache_instruction_t> **** ICACHE_RSP_INSTRUCTION;//[nb_entity][icache_dedicated_nb_port][iaccess_nb_instruction] 43 public : sc_out<morpheo::Ticache_error_t > *** ICACHE_RSP_ERROR ;//[nb_entity][icache_dedicated_nb_port] 44 44 45 public : sc_in < Tcontrol_t > *** DCACHE_REQ_VAL ;46 public : sc_out< Tcontrol_t > *** DCACHE_REQ_ACK ;47 public : sc_in < Tdcache_context_t > *** DCACHE_REQ_CONTEXT_ID ;48 public : sc_in < Tdcache_packet_t > *** DCACHE_REQ_PACKET_ID ;49 public : sc_in < Tdcache_address_t > *** DCACHE_REQ_ADDRESS ;50 public : sc_in < Tdcache_type_t > *** DCACHE_REQ_TYPE ;51 public : sc_in < Tdcache_data_t > *** DCACHE_REQ_WDATA ;45 public : sc_in <morpheo::Tcontrol_t > *** DCACHE_REQ_VAL ;//[nb_entity][dcache_dedicated_nb_port] 46 public : sc_out<morpheo::Tcontrol_t > *** DCACHE_REQ_ACK ;//[nb_entity][dcache_dedicated_nb_port] 47 public : sc_in <morpheo::Tdcache_context_t > *** DCACHE_REQ_CONTEXT_ID ;//[nb_entity][dcache_dedicated_nb_port] 48 public : sc_in <morpheo::Tdcache_packet_t > *** DCACHE_REQ_PACKET_ID ;//[nb_entity][dcache_dedicated_nb_port] 49 public : sc_in <morpheo::Tdcache_address_t > *** DCACHE_REQ_ADDRESS ;//[nb_entity][dcache_dedicated_nb_port] 50 public : sc_in <morpheo::Tdcache_type_t > *** DCACHE_REQ_TYPE ;//[nb_entity][dcache_dedicated_nb_port] 51 public : sc_in <morpheo::Tdcache_data_t > *** DCACHE_REQ_WDATA ;//[nb_entity][dcache_dedicated_nb_port] 52 52 53 public : sc_out< Tcontrol_t > *** DCACHE_RSP_VAL ;54 public : sc_in < Tcontrol_t > *** DCACHE_RSP_ACK ;55 public : sc_out< Tdcache_context_t > *** DCACHE_RSP_CONTEXT_ID ;56 public : sc_out< Tdcache_packet_t > *** DCACHE_RSP_PACKET_ID ;57 public : sc_out< Tdcache_data_t > *** DCACHE_RSP_RDATA ;58 public : sc_out< Tdcache_error_t > *** DCACHE_RSP_ERROR ;53 public : sc_out<morpheo::Tcontrol_t > *** DCACHE_RSP_VAL ;//[nb_entity][dcache_dedicated_nb_port] 54 public : sc_in <morpheo::Tcontrol_t > *** DCACHE_RSP_ACK ;//[nb_entity][dcache_dedicated_nb_port] 55 public : sc_out<morpheo::Tdcache_context_t > *** DCACHE_RSP_CONTEXT_ID ;//[nb_entity][dcache_dedicated_nb_port] 56 public : sc_out<morpheo::Tdcache_packet_t > *** DCACHE_RSP_PACKET_ID ;//[nb_entity][dcache_dedicated_nb_port] 57 public : sc_out<morpheo::Tdcache_data_t > *** DCACHE_RSP_RDATA ;//[nb_entity][dcache_dedicated_nb_port] 58 public : sc_out<morpheo::Tdcache_error_t > *** DCACHE_RSP_ERROR ;//[nb_entity][dcache_dedicated_nb_port] 59 59 60 60 // ===== [ Internal ]==================================================== 61 public : Tcontrol_t ** icache_req_ack ;62 public : Tcontrol_t ** icache_rsp_val ;63 public : Tcontrol_t ** dcache_req_ack ;64 public : Tcontrol_t ** dcache_rsp_val ;61 public : morpheo::Tcontrol_t ** icache_req_ack ; 62 public : morpheo::Tcontrol_t ** icache_rsp_val ; 63 public : morpheo::Tcontrol_t ** dcache_req_ack ; 64 public : morpheo::Tcontrol_t ** dcache_rsp_val ; 65 65 66 66 // ===== [ Variables ]=================================================== … … 68 68 private : Parameters * param; 69 69 70 private: char ** read_iram; 71 private: char ** read_dram; 72 private: char * write_dram; 70 private : char ** read_iram; 71 private : char ** read_dram; 72 private : char * write_dram; 73 74 private : bool * context_stop; // to determine which context have send the signal stop (a same thread can send many signal) 75 private : uint32_t nb_context_stop; // stop the simulation when all context have send the stop signal 76 73 77 74 78 // ===== [ Components ]================================================== … … 88 92 public : ~Environment (void); 89 93 90 public : bool init (std::string section, const char * filename, const char ** list_section); 91 public : void reset (void); 94 public : bool init (std::string section, const char * filename, const char ** list_section); 95 public : void reset (void); 96 public : void stop (uint32_t num_context); 97 public : bool simulation_end (void); 92 98 93 public : void transition (void);94 public : void genMoore (void);99 public : void transition (void); 100 public : void genMoore (void); 95 101 96 102 public : friend std::ostream& operator<< (std::ostream& output, Environment &x); … … 137 143 } 138 144 }; 139 140 141 // private: bool * context_stop; // to determine which context have send the signal stop (a same thread can send many signal)142 // private: uint3 nb_context_stop; // stop the simulation when all context have send the stop signal143 144 // //---------------------------------------------------------------------------------------------145 // //-----[ stop ]--------------------------------------------------------------------------------146 // //---------------------------------------------------------------------------------------------147 // public : bool stop ()148 // {149 // return (nb_context_stop >= nb_context);150 // }151 152 145 }; 153 146 -
trunk/IPs/systemC/Environment/include/Environment_Parameters.h
r81 r88 8 8 #include "../RamLock/include/RamLock_Parameters.h" 9 9 #include "../Sim2OS/include/Sim2OS_Parameters.h" 10 #include "../../processor/Morpheo/Common/include/ToString.h" 10 11 11 12 namespace environment { … … 13 14 class Parameters 14 15 { 15 public : uint32_t nb_iport;16 public : uint32_t nb_dport;17 public : uint32_t nb_entity;18 public : uint32_t * icache_dedicated_nb_port;19 public : uint32_t * dcache_dedicated_nb_port;20 21 public : uint32_t * iaccess_nb_context ;22 public : uint32_t * iaccess_nb_packet ;23 public : uint32_t * iaccess_size_address ;24 public : uint32_t * iaccess_nb_instruction;25 public : uint32_t * iaccess_size_instruction;26 27 public : uint32_t * daccess_nb_context ;28 public : uint32_t * daccess_nb_packet ;29 public : uint32_t * daccess_size_address ;30 public : uint32_t * daccess_size_data ;16 public : uint32_t nb_iport ; 17 public : uint32_t nb_dport ; 18 public : uint32_t nb_entity ; 19 public : uint32_t * icache_dedicated_nb_port; //[nb_entity] 20 public : uint32_t * dcache_dedicated_nb_port; //[nb_entity] 21 22 public : uint32_t * iaccess_nb_context ; //[nb_entity] 23 public : uint32_t * iaccess_nb_packet ; //[nb_entity] 24 public : uint32_t * iaccess_size_address ; //[nb_entity] 25 public : uint32_t * iaccess_nb_instruction ; //[nb_entity] 26 public : uint32_t * iaccess_size_instruction; //[nb_entity] 27 28 public : uint32_t * daccess_nb_context ; //[nb_entity] 29 public : uint32_t * daccess_nb_packet ; //[nb_entity] 30 public : uint32_t * daccess_size_address ; //[nb_entity] 31 public : uint32_t * daccess_size_data ; //[nb_entity] 31 32 32 33 // Parameters cache 33 public : cache::Parameters * param_cache;34 public : cache::Parameters * param_cache ; 34 35 // Parameters tty 35 public : uint32_t nb_component_tty;36 public : uint32_t * tty_address;37 public : tty::Parameters ** param_tty;36 public : uint32_t nb_component_tty ; 37 public : uint32_t * tty_address ; //[nb_component_tty] 38 public : tty::Parameters ** param_tty ; //[nb_component_tty] 38 39 // Parameters ramlock 39 public : uint32_t nb_component_ramlock;40 public : uint32_t * ramlock_address;41 public : ramlock::Parameters ** param_ramlock;40 public : uint32_t nb_component_ramlock ; 41 public : uint32_t * ramlock_address ; //[nb_component_ramlock] 42 public : ramlock::Parameters ** param_ramlock ; //[nb_component_ramlock] 42 43 // Parameters sim2OS 43 public : uint32_t sim2os_address;44 public : uint32_t sim2os_size;45 public : sim2os::Parameters * param_sim2os;44 public : uint32_t sim2os_address ; 45 public : uint32_t sim2os_size ; 46 public : sim2os::Parameters * param_sim2os ; 46 47 // Parameters data 47 public : data::Parameters * param_data;48 public : data::Parameters * param_data ; 48 49 49 50 // Parameters buffer_respons 50 public : queue::Parameters ** param_buffer_irsp;51 public : queue::Parameters ** param_buffer_drsp;51 public : queue::Parameters ** param_buffer_irsp ; //[nb_entity] 52 public : queue::Parameters ** param_buffer_drsp ; //[nb_entity] 52 53 53 54 public : Parameters (// General … … 232 233 delete param_cache; 233 234 } 235 236 public : std::string print (uint32_t depth) 237 { 238 std::string tab = std::string(depth,'\t'); 239 std::string str = ""; 240 241 str+=tab+"nb_entity : "+morpheo::toString(nb_entity)+"\n"; 242 str+=tab+"nb_iport : "+morpheo::toString(nb_iport )+"\n"; 243 str+=tab+"nb_dport : "+morpheo::toString(nb_dport )+"\n"; 244 for (uint32_t i=0; i<nb_entity; ++i) 245 { 246 str+=tab+"ENTITY ["+morpheo::toString(i)+"]\n"; 247 str+=tab+" * icache_dedicated_nb_port : "+morpheo::toString(icache_dedicated_nb_port[i])+"\n"; 248 str+=tab+" * dcache_dedicated_nb_port : "+morpheo::toString(dcache_dedicated_nb_port[i])+"\n"; 249 str+=tab+" * iaccess_nb_context : "+morpheo::toString(iaccess_nb_context [i])+"\n"; 250 str+=tab+" * iaccess_nb_packet : "+morpheo::toString(iaccess_nb_packet [i])+"\n"; 251 str+=tab+" * iaccess_size_address : "+morpheo::toString(iaccess_size_address [i])+"\n"; 252 str+=tab+" * iaccess_nb_instruction : "+morpheo::toString(iaccess_nb_instruction [i])+"\n"; 253 str+=tab+" * iaccess_size_instruction : "+morpheo::toString(iaccess_size_instruction[i])+"\n"; 254 str+=tab+" * daccess_nb_context : "+morpheo::toString(daccess_nb_context [i])+"\n"; 255 str+=tab+" * daccess_nb_packet : "+morpheo::toString(daccess_nb_packet [i])+"\n"; 256 str+=tab+" * daccess_size_address : "+morpheo::toString(daccess_size_address [i])+"\n"; 257 str+=tab+" * daccess_size_data : "+morpheo::toString(daccess_size_data [i])+"\n"; 258 } 259 260 str+=tab+"CACHE\n"; 261 str+=param_cache->print(depth+1); 262 263 // str+=tab+"nb_component_tty : "+morpheo::toString(nb_component_tty )+"\n"; 264 // for (uint32_t i=0; i<nb_component_tty; ++i) 265 // { 266 // str+=tab+"TTY ["+morpheo::toString(i)+"]\n"; 267 // str+=tab+" * tty_address : "+morpheo::toString(tty_address [i])+"\n"; 268 // str+=param_tty->print(depth+1); 269 // } 270 271 // str+=tab+"nb_component_ramlock : "+morpheo::toString(nb_component_ramlock )+"\n"; 272 // for (uint32_t i=0; i<nb_component_ramlock; ++i) 273 // { 274 // str+=tab+"RAMLOCK ["+morpheo::toString(i)+"]\n"; 275 // str+=tab+" * ramlock_address : "+morpheo::toString(ramlock_address [i])+"\n"; 276 // str+=param_ramlock->print(depth+1); 277 // } 278 279 // str+=tab+"SIM2OS\n"; 280 // str+=tab+"sim2os_address : "+morpheo::toString(sim2os_address)+"\n"; 281 // str+=tab+"sim2os_size : "+morpheo::toString(sim2os_size )+"\n"; 282 // str+=param_sim2os->print(depth+1); 283 284 // str+=tab+"DATA\n"; 285 // str+=param_data->print(depth+1); 286 287 // for (uint32_t i=0; i<nb_entity; ++i) 288 // { 289 // str+=tab+"BUFFER_IRSP ["+morpheo::toString(i)+"]\n"; 290 // str+=param_buffer_irsp[i]_data->print(depth+1); 291 // } 292 293 // for (uint32_t i=0; i<nb_entity; ++i) 294 // { 295 // str+=tab+"BUFFER_DRSP ["+morpheo::toString(i)+"]\n"; 296 // str+=param_buffer_drsp[i]_data->print(depth+1); 297 // } 298 299 return str; 300 } 301 302 // public : friend std::ostream& operator<< (std::ostream& output, const Parameters &x) 303 // { 304 // x.print(0); 305 // return output; 306 // } 234 307 }; 235 308 -
trunk/IPs/systemC/Environment/include/Types.h
r81 r88 2 2 #define ENVIRONMENT_TYPES_H 3 3 4 #include "../../processor/Morpheo/ Behavioural/include/Types.h"4 #include "../../processor/Morpheo/TopLevel/include/Types.h" 5 5 #include "../../processor/Morpheo/Behavioural/include/Constants.h" 6 6 #include "../Cache/include/Types.h" … … 9 9 { 10 10 11 typedef morpheo::behavioural::Tcontrol_t Tcontrol_t ;11 // typedef morpheo::behavioural::Tcontrol_t Tcontrol_t ; 12 12 13 typedef morpheo::behavioural::Tcontext_t Ticache_context_t ;14 typedef morpheo::behavioural::Tpacket_t Ticache_packet_t ;15 typedef morpheo::behavioural::Ticache_address_t Ticache_address_t ;16 typedef morpheo::behavioural::Ticache_type_t Ticache_type_t ;17 typedef morpheo::behavioural::Ticache_instruction_t Ticache_instruction_t;18 typedef morpheo::behavioural::Ticache_error_t Ticache_error_t ;13 // typedef morpheo::behavioural::Tcontext_t Ticache_context_t ; 14 // typedef morpheo::behavioural::Tpacket_t Ticache_packet_t ; 15 // typedef morpheo::behavioural::Ticache_address_t Ticache_address_t ; 16 // typedef morpheo::behavioural::Ticache_type_t Ticache_type_t ; 17 // typedef morpheo::behavioural::Ticache_instruction_t Ticache_instruction_t; 18 // typedef morpheo::behavioural::Ticache_error_t Ticache_error_t ; 19 19 20 typedef morpheo::behavioural::Tcontext_t Tdcache_context_t ; 21 typedef morpheo::behavioural::Tpacket_t Tdcache_packet_t ; 22 typedef morpheo::behavioural::Tdcache_address_t Tdcache_address_t ; 23 typedef morpheo::behavioural::Tdcache_type_t Tdcache_type_t ; 24 typedef morpheo::behavioural::Tdcache_data_t Tdcache_data_t ; 25 typedef morpheo::behavioural::Tdcache_error_t Tdcache_error_t ; 20 // typedef morpheo::behavioural::Tcontext_t Tdcache_context_t ; 21 // typedef morpheo::behavioural::Tpacket_t Tdcache_packet_t ; 22 // typedef morpheo::behavioural::Tdcache_address_t Tdcache_address_t ; 23 // typedef morpheo::behavioural::Tdcache_type_t Tdcache_type_t ; 24 // typedef morpheo::behavioural::Tdcache_data_t Tdcache_data_t ; 25 // typedef morpheo::behavioural::Tdcache_error_t Tdcache_error_t ; 26 26 27 }; 27 28 #endif
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