Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (16 years ago)
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- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r81 r88 255 255 // Interface "MEMORY_IN" 256 256 //================================================================ 257 258 if ((PORT_READ(in_MEMORY_IN_VAL ) == 1) and257 258 if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and 259 259 ( internal_MEMORY_IN_ACK == 1)) 260 260 { … … 266 266 267 267 #ifdef DEBUG_TEST 268 if (PORT_READ(in_MEMORY_IN_TYPE ) != TYPE_MEMORY)268 if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY) 269 269 throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'"); 270 270 #endif 271 Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION );272 Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT ) +273 PORT_READ(in_MEMORY_IN_DATA_RA ));271 Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]); 272 Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) + 273 PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT])); 274 274 bool exception_alignement = (mask_memory_access(operation) & address) != 0; 275 275 … … 287 287 288 288 // Write pointer is define in rename stage : 289 Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE );289 Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 290 290 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); 291 291 … … 375 375 log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); 376 376 377 _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID );378 _store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID );379 _store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID );380 _store_queue [index]._packet_id = (not _param->_have_port_ packet_id )?0:PORT_READ(in_MEMORY_IN_PACKET_ID);377 _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); 378 _store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); 379 _store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); 380 _store_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); 381 381 _store_queue [index]._operation = operation; 382 _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE );382 _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 383 383 _store_queue [index]._address = address; 384 384 385 385 // reordering data 386 _store_queue [index]._wdata = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB ), memory_size(operation), 0);387 // _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD );386 _store_queue [index]._wdata = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); 387 // _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); 388 388 } 389 389 } … … 413 413 // NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits) 414 414 _speculative_access_queue [index]._state = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE; 415 _speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID );416 _speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID );417 _speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID );418 _speculative_access_queue [index]._packet_id = (not _param->_have_port_ packet_id )?0:PORT_READ(in_MEMORY_IN_PACKET_ID);415 _speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); 416 _speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); 417 _speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); 418 _speculative_access_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); 419 419 420 420 _speculative_access_queue [index]._operation = operation; 421 _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE );422 _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE );421 _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 422 _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 423 423 _speculative_access_queue [index]._address = address; 424 424 // NOTE : is operation is a load, then they are a result and must write in the register file 425 425 _speculative_access_queue [index]._write_rd = is_operation_memory_load(operation); 426 _speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD );426 _speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); 427 427 428 428 _speculative_access_queue [index]._exception = exception; … … 437 437 438 438 if (( internal_MEMORY_OUT_VAL == 1) and 439 (PORT_READ(in_MEMORY_OUT_ACK ) == 1))439 (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) 440 440 { 441 441 log_printf(TRACE,Load_store_unit,FUNCTION,"MEMORY_OUT transaction"); … … 495 495 496 496 if (( internal_DCACHE_REQ_VAL == 1) and 497 (PORT_READ(in_DCACHE_REQ_ACK ) == 1))497 (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) 498 498 { 499 499 log_printf(TRACE,Load_store_unit,FUNCTION,"DCACHE_REQ"); … … 598 598 // Interface "DCACHE_RSP" 599 599 //================================================================ 600 if ((PORT_READ(in_DCACHE_RSP_VAL )== 1) and600 if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and 601 601 ( internal_DCACHE_RSP_ACK == 1)) 602 602 { … … 604 604 605 605 // don't use context_id : because there are one queue for all thread 606 //Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID );607 Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID );608 Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA );609 Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR );606 //Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); 607 Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]); 608 Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA [0]); 609 Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); 610 610 611 611 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); … … 662 662 663 663 664 #if DEBUG>=DEBUG_TRACE664 #if defined(DEBUG) and (DEBUG>=DEBUG_TRACE) 665 665 // ***** dump store queue 666 666 std::cout << "Dump STORE_QUEUE :" << std::endl … … 694 694 << _load_queue[j] << std::endl; 695 695 } 696 697 696 #endif 698 697 699 698 #ifdef STATISTICS 700 for (uint32_t i=0; i<_param->_size_store_queue; i++) 701 if (_store_queue[i]._state != STORE_QUEUE_EMPTY) 702 (*_stat_use_store_queue) ++; 703 for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) 704 if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY) 705 (*_stat_use_speculative_access_queue) ++; 706 for (uint32_t i=0; i<_param->_size_load_queue; i++) 707 if (_load_queue[i]._state != LOAD_QUEUE_EMPTY) 708 (*_stat_use_load_queue) ++; 699 if (usage_is_set(_usage,USE_STATISTICS)) 700 { 701 for (uint32_t i=0; i<_param->_size_store_queue; i++) 702 if (_store_queue[i]._state != STORE_QUEUE_EMPTY) 703 (*_stat_use_store_queue) ++; 704 for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) 705 if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY) 706 (*_stat_use_speculative_access_queue) ++; 707 for (uint32_t i=0; i<_param->_size_load_queue; i++) 708 if (_load_queue[i]._state != LOAD_QUEUE_EMPTY) 709 (*_stat_use_load_queue) ++; 710 } 709 711 #endif 710 712 }
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