Ignore:
Timestamp:
Dec 10, 2008, 7:31:39 PM (16 years ago)
Author:
rosiere
Message:

Almost complete design
with Test and test platform

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src
Files:
8 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management.cpp

    r81 r88  
    3838    log_printf(FUNC,Address_management,FUNCTION,"Begin");
    3939
     40#if DEBUG_Address_management == true
     41    log_printf(INFO,Address_management,FUNCTION,_("<%s> Parameters"),_name.c_str());
     42
     43    std::cout << *param << std::endl;
     44#endif   
     45
    4046    log_printf(INFO,Address_management,FUNCTION,"Allocation");
    4147
    … …  
    4753
    4854#ifdef STATISTICS
    49     if (_usage & USE_STATISTICS)
     55    if (usage_is_set(_usage,USE_STATISTICS))
    5056      {
    5157        log_printf(INFO,Address_management,FUNCTION,"Allocation of statistics");
    … …  
    5662
    5763#ifdef VHDL
    58     if (_usage & USE_VHDL)
     64    if (usage_is_set(_usage,USE_VHDL))
    5965      {
    6066        // generate the vhdl
    … …  
    6672
    6773#ifdef SYSTEMC
    68     if (_usage & USE_SYSTEMC)
     74    if (usage_is_set(_usage,USE_SYSTEMC))
    6975      {
    7076        // Affect output constant
    … …  
    94100#endif
    95101      }
     102
    96103    log_printf(FUNC,Address_management,FUNCTION,"End");
    97104  };
    … …  
    104111
    105112#ifdef STATISTICS
    106     if (_usage & USE_STATISTICS)
     113    if (usage_is_set(_usage,USE_STATISTICS))
    107114      {
    108115        statistics_deallocation();

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp

    r81 r88  
    6262      ALLOC_VALACK_OUT (out_ADDRESS_VAL                        ,VAL);
    6363      ALLOC_VALACK_IN  ( in_ADDRESS_ACK                        ,ACK);
    64       ALLOC_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t,_param->_size_address                 );
    65       ALLOC_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr         );
     64      ALLOC_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t,_param->_size_instruction_address     );
     65      ALLOC_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr         );
    6666      ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state            );
    67       ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
     67      ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
    6868    }
    6969
    … …  
    8080      ALLOC_VALACK_OUT (out_PREDICT_VAL                        ,VAL);
    8181      ALLOC_VALACK_IN  ( in_PREDICT_ACK                        ,ACK);
    82       ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_address);
    83       ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_address);
     82      ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_instruction_address);
     83      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_instruction_address);
    8484      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"pc_current_is_ds_take"      ,Tcontrol_t        ,1);
    85       ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_address);
     85      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_instruction_address);
    8686      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,"pc_next_is_ds_take"         ,Tcontrol_t        ,1);
    87       ALLOC_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr);
     87      ALLOC_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
    8888      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
    89       ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
     89      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
    9090    }
    9191    {
    … …  
    9999      ALLOC_INTERFACE("event", IN, SOUTH, "Event (miss, exception ...)");
    100100
    101       ALLOC_VALACK_IN ( in_EVENT_VAL    ,VAL);
    102       ALLOC_VALACK_OUT(out_EVENT_ACK    ,ACK);
    103       ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS,"address",Tgeneral_address_t,_param->_size_address);
     101      ALLOC_VALACK_IN ( in_EVENT_VAL          ,VAL);
     102      ALLOC_VALACK_OUT(out_EVENT_ACK          ,ACK);
     103      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS         ,"address"         ,Tgeneral_address_t,_param->_size_instruction_address);
     104      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT    ,"address_next"    ,Tgeneral_address_t,_param->_size_instruction_address);
     105      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"address_next_val",Tcontrol_t,1);
     106      ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE      ,"is_ds_take"      ,Tcontrol_t,1);
    104107    }
    105108
     109    // ~~~~~[ Internal  ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
     110    if (usage_is_set(_usage,USE_SYSTEMC))
     111      {
     112        reg_PC_CURRENT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction];
     113        reg_PC_NEXT_INSTRUCTION_ENABLE    = new Tcontrol_t [_param->_nb_instruction];
     114      }
     115
    106116    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    107     reg_PC_CURRENT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction];
    108     reg_PC_NEXT_INSTRUCTION_ENABLE    = new Tcontrol_t [_param->_nb_instruction];
    109 
    110117#ifdef POSITION
    111     _component->generate_file();
     118     if (usage_is_set(_usage,USE_POSITION))
     119       _component->generate_file();
    112120#endif
    113121

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp

    r81 r88  
    2323    log_printf(FUNC,Address_management,FUNCTION,"Begin");
    2424
    25     if (_usage & USE_SYSTEMC)
     25    if (usage_is_set(_usage,USE_SYSTEMC))
    2626      {
    2727        delete    in_CLOCK ;
    … …  
    3232        delete    out_ADDRESS_INSTRUCTION_ADDRESS        ;
    3333        delete [] out_ADDRESS_INSTRUCTION_ENABLE         ;
    34         if (_param->_have_port_instruction_ptr)
     34        if (_param->_have_port_inst_ifetch_ptr)
    3535        delete    out_ADDRESS_INST_IFETCH_PTR            ;
    3636        delete    out_ADDRESS_BRANCH_STATE               ;
    37         if (_param->_have_port_branch_update_prediction_id)
     37        if (_param->_have_port_depth)
    3838        delete    out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
    3939        delete    out_PREDICT_VAL                        ;
    … …  
    4545        delete     in_PREDICT_PC_NEXT_IS_DS_TAKE         ;
    4646        delete []  in_PREDICT_INSTRUCTION_ENABLE         ;
    47         if (_param->_have_port_instruction_ptr)
     47        if (_param->_have_port_inst_ifetch_ptr)
    4848        delete     in_PREDICT_INST_IFETCH_PTR            ;
    4949        delete     in_PREDICT_BRANCH_STATE               ;
    50         if (_param->_have_port_branch_update_prediction_id)
     50        if (_param->_have_port_depth)
    5151        delete     in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
    5252        delete     in_EVENT_VAL                          ;
    5353        delete    out_EVENT_ACK                          ;
    5454        delete     in_EVENT_ADDRESS                      ;
     55        delete     in_EVENT_ADDRESS_NEXT                 ;
     56        delete     in_EVENT_ADDRESS_NEXT_VAL             ;
     57        delete     in_EVENT_IS_DS_TAKE                   ;
     58     
     59        // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
     60        if (usage_is_set(_usage,USE_SYSTEMC))
     61          {
     62            delete reg_PC_CURRENT_INSTRUCTION_ENABLE;
     63            delete reg_PC_NEXT_INSTRUCTION_ENABLE   ;
     64          }
    5565      }
    5666
    57     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    58     delete reg_PC_CURRENT_INSTRUCTION_ENABLE;
    59     delete reg_PC_NEXT_INSTRUCTION_ENABLE   ;
    6067
    6168    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_end_cycle.cpp

    r81 r88  
    2525
    2626#ifdef STATISTICS
    27     _stat->end_cycle();
     27    if (usage_is_set(_usage,USE_STATISTICS))
     28      _stat->end_cycle();
    2829#endif   
    2930
    … …  
    3132    // Evaluation before read the ouput signal
    3233//  sc_start(0);
    33     _interfaces->testbench();
     34    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
     35      _interfaces->testbench();
    3436#endif
    3537

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp

    r84 r88  
    3232    PORT_WRITE(out_ADDRESS_VAL                        ,internal_ADDRESS_VAL                      );
    3333    PORT_WRITE(out_ADDRESS_INSTRUCTION_ADDRESS        ,reg_PC_CURRENT                            );
    34     if (_param->_have_port_instruction_ptr)
     34    if (_param->_have_port_inst_ifetch_ptr)
    3535    PORT_WRITE(out_ADDRESS_INST_IFETCH_PTR            ,reg_PC_CURRENT_INST_IFETCH_PTR            );
    3636    PORT_WRITE(out_ADDRESS_BRANCH_STATE               ,reg_PC_CURRENT_BRANCH_STATE               );
    37     if (_param->_have_port_branch_update_prediction_id)
     37    if (_param->_have_port_depth)
    3838    PORT_WRITE(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID);
    3939

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp

    r84 r88  
    2222  void Address_management::transition (void)
    2323  {
    24     log_printf(FUNC,Address_management,FUNCTION,"Begin");
     24    log_begin(Address_management,FUNCTION);
     25    log_function(Address_management,FUNCTION,_name.c_str());
    2526
    2627    if (PORT_READ(in_NRESET) == 0)
    … …  
    2829        // nothing is valid
    2930        reg_PC_CURRENT_VAL   = 0;
    30         reg_PC_NEXT_VAL      = 0;
     31
     32        reg_PC_NEXT_VAL      = 1;
     33        reg_PC_NEXT          = 0x100>>2;
     34
    3135        reg_PC_NEXT_NEXT_VAL = 0;
    3236      }
    … …  
    4044            for (uint32_t i=0; i<_param->_nb_instruction; i++)
    4145            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
    42             if (_param->_have_port_instruction_ptr)
     46            if (_param->_have_port_inst_ifetch_ptr)
    4347            reg_PC_NEXT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
    4448            reg_PC_NEXT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
    45             if (_param->_have_port_branch_update_prediction_id)
     49            if (_param->_have_port_depth)
    4650            reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
    4751           
    … …  
    5155
    5256#ifdef STATISTICS
    53             (*_stat_nb_transaction_predict) ++;
     57            if (usage_is_set(_usage,USE_STATISTICS))
     58              (*_stat_nb_transaction_predict) ++;
    5459#endif
    5560          }
    … …  
    6267          {
    6368#ifdef STATISTICS
    64             if (reg_PC_CURRENT_VAL)
    65               {
    66                 (*_stat_nb_transaction_address) ++;
    67 
    68                 for (uint32_t i=0; i<_param->_nb_instruction; i++)
    69                   if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true)
    70                     (*_stat_sum_packet_size) ++;
    71               }
     69            if (usage_is_set(_usage,USE_STATISTICS))
     70              if (reg_PC_CURRENT_VAL)
     71                {
     72                  (*_stat_nb_transaction_address) ++;
     73                 
     74                  for (uint32_t i=0; i<_param->_nb_instruction; i++)
     75                    if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true)
     76                      (*_stat_sum_packet_size) ++;
     77                }
    7278#endif
    7379
    … …  
    110116        if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK)
    111117          {
    112             log_printf(TRACE,Address_management,FUNCTION,"EVENT : Transaction");
     118            log_printf(TRACE,Address_management,FUNCTION,"  * EVENT : Transaction");
     119            log_printf(TRACE,Address_management,FUNCTION,"    * IS_DS_TAKE       : %d"  ,PORT_READ(in_EVENT_IS_DS_TAKE      ));
     120            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS          : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS         ),PORT_READ(in_EVENT_ADDRESS         )<<2);
     121            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT     : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT    ),PORT_READ(in_EVENT_ADDRESS_NEXT    )<<2);
     122            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT_VAL : %d"  ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL));
    113123            reg_PC_CURRENT_VAL                      = 0;
    114124            reg_PC_NEXT_VAL                         = 1;
    … …  
    118128            //  * load   miss speculation : the load is execute, the event_address is the next address (also the destination of branch)
    119129            //  * exception               : goto the first instruction of exception handler (also is not in delay slot).
    120             reg_PC_NEXT_IS_DS_TAKE                  = 0;
     130
     131            reg_PC_NEXT_IS_DS_TAKE                  = PORT_READ(in_EVENT_IS_DS_TAKE);
    121132//          reg_PC_NEXT_INST_IFETCH_PTR             = 0;
    122133//          reg_PC_NEXT_BRANCH_STATE                = BRANCH_STATE_NONE;
    123134//          reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
    124135           
    125 //          reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
    126 //          for (uint32_t i=1; i<_param->_nb_instruction; i++)
    127 //            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0;
     136            reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
     137            for (uint32_t i=1; i<_param->_nb_instruction; i++)
     138              reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0;
    128139
    129             reg_PC_NEXT_NEXT_VAL                    = 0; // cancel all prediction (event is send at the predict unit)
     140            reg_PC_NEXT_NEXT_VAL                    = PORT_READ(in_EVENT_ADDRESS_NEXT_VAL);
     141            reg_PC_NEXT_NEXT                        = PORT_READ(in_EVENT_ADDRESS_NEXT);
     142            reg_PC_NEXT_NEXT_IS_DS_TAKE             = 0;//??
     143
     144            // Note : is_ds_take = address_next_val
     145            // Because, is not ds take, can continue in sequence
     146
     147#ifdef DEBUG_TEST
     148            if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE))
     149              throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take"));
     150#endif
    130151
    131152#ifdef STATISTICS
    132             (*_stat_nb_transaction_event) ++;
     153            if (usage_is_set(_usage,USE_STATISTICS))
     154              (*_stat_nb_transaction_event) ++;
    133155#endif
    134156          }
    135157      }
    136158
    137 #if DEBUG >= DEBUG_TRACE
    138     log_printf(TRACE,Address_management,FUNCTION,"Address_Management : ");
    139     log_printf(TRACE,Address_management,FUNCTION,"Current   : %d %d 0x%x",reg_PC_CURRENT_VAL, reg_PC_CURRENT_IS_DS_TAKE, reg_PC_CURRENT);
    140     log_printf(TRACE,Address_management,FUNCTION,"Next      : %d %d 0x%x",reg_PC_NEXT_VAL, reg_PC_NEXT_IS_DS_TAKE, reg_PC_NEXT);   
    141     log_printf(TRACE,Address_management,FUNCTION,"Next_Next : %d %d 0x%x",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT);   
     159#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
     160    log_printf(TRACE,Address_management,FUNCTION,"  * Dump PC");
     161    log_printf(TRACE,Address_management,FUNCTION,"    * Current   : %d %d 0x%.8x (%.8x)",reg_PC_CURRENT_VAL  , reg_PC_CURRENT_IS_DS_TAKE  , reg_PC_CURRENT  , reg_PC_CURRENT  <<2);
     162    log_printf(TRACE,Address_management,FUNCTION,"    * Next      : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_VAL     , reg_PC_NEXT_IS_DS_TAKE     , reg_PC_NEXT     , reg_PC_NEXT     <<2);   
     163    log_printf(TRACE,Address_management,FUNCTION,"    * Next_Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT, reg_PC_NEXT_NEXT<<2);   
    142164#endif
    143165
    … …  
    145167    end_cycle ();
    146168#endif
    147 
    148     log_printf(FUNC,Address_management,FUNCTION,"End");
     169   
     170    log_end(Address_management,FUNCTION);
    149171  };
    150172

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Parameters.cpp

    r81 r88  
    2121  Parameters::Parameters (uint32_t nb_instruction,
    2222                          uint32_t size_address  ,
    23                           uint32_t size_branch_update_prediction)
     23                          uint32_t size_branch_update_prediction,
     24                          bool     is_toplevel)
    2425  {
    2526    log_printf(FUNC,Address_management,FUNCTION,"Begin");
    2627
    27     _nb_instruction                        = nb_instruction               ;
    28     _size_address                          = size_address                 ;
    29     _size_branch_update_prediction         = size_branch_update_prediction;
    30 
    31     _size_instruction_ptr                  = log2(nb_instruction);
    32 
    33     _have_port_instruction_ptr             = _size_instruction_ptr > 0;
    34     _have_port_branch_update_prediction_id = size_branch_update_prediction > 0;
     28    _nb_instruction = nb_instruction               ;
    3529
    3630    test();
     31
     32    if (is_toplevel)
     33      {
     34        _size_instruction_address  = size_address                 ;
     35        _size_depth                = size_branch_update_prediction;
     36        _size_inst_ifetch_ptr      = log2(nb_instruction);
     37       
     38        _have_port_inst_ifetch_ptr = _size_inst_ifetch_ptr > 0;
     39        _have_port_depth           = _size_depth > 0;
     40
     41        copy();
     42      }
     43
    3744    log_printf(FUNC,Address_management,FUNCTION,"End");
    3845  };
    … …  
    5562  };
    5663
     64#undef  FUNCTION
     65#define FUNCTION "Address_management::copy"
     66  void Parameters::copy (void)
     67  {
     68    log_printf(FUNC,Address_management,FUNCTION,"Begin");
     69    log_printf(FUNC,Address_management,FUNCTION,"End");
     70  };
     71
    5772}; // end namespace address_management
    5873}; // end namespace ifetch_unit

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Parameters_print.cpp

    r81 r88  
    2424    log_printf(FUNC,Address_management,FUNCTION,"Begin");
    2525
    26     XML xml ("address_management");
     26//     XML xml ("address_management");
    2727
    28     xml.balise_open("address_management");
    29     xml.singleton_begin("nb_instruction               "); xml.attribut("value",toString(_nb_instruction               )); xml.singleton_end();
    30     xml.singleton_begin("size_address                 "); xml.attribut("value",toString(_size_address                 )); xml.singleton_end();
    31     xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
    32     xml.balise_close();
     28//     xml.balise_open("address_management");
     29//     xml.singleton_begin("nb_instruction               "); xml.attribut("value",toString(_nb_instruction               )); xml.singleton_end();
     30// //  xml.singleton_begin("size_address                 "); xml.attribut("value",toString(_size_address                 )); xml.singleton_end();
     31// //  xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
     32//     xml.balise_close();
     33
     34//     return xml.get_body(depth);
     35
     36    std::string str = "";
    3337
    3438    log_printf(FUNC,Address_management,FUNCTION,"End");
    35    
    36     return xml.get_body(depth);
     39
     40    return str;
    3741  };
    3842
Note: See TracChangeset for help on using the changeset viewer.