Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register
- Files:
-
- 1 added
- 19 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/Makefile.deps
r81 r88 16 16 #-----[ Directory ]---------------------------------------- 17 17 18 Branch_Target_Buffer_Register_DIR 18 Branch_Target_Buffer_Register_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register 19 19 20 20 #-----[ Library ]------------------------------------------ 21 21 22 22 Branch_Target_Buffer_Register_LIBRARY = -lBranch_Target_Buffer_Register \ 23 23 $(Behavioural_LIBRARY) 24 24 25 Branch_Target_Buffer_Register_DIR_LIBRARY 26 25 Branch_Target_Buffer_Register_DIR_LIBRARY = -L$(Branch_Target_Buffer_Register_DIR)/lib \ 26 $(Behavioural_DIR_LIBRARY) 27 27 28 28 #-----[ Rules ]-------------------------------------------- -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/Makefile
r81 r88 24 24 library_clean : Branch_Target_Buffer_Register_library_clean 25 25 26 local_clean : 27 26 28 include $(DIR_COMPONENT)/Makefile.deps 27 29 include $(DIR_MORPHEO)/Behavioural/Makefile.flags -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg
r82 r88 4 4 1 1 *4 # size_buffer 5 5 1 1 *4 # associativity 6 3 2 32*2 # size_address6 30 30 *2 # size_address 7 7 2 2 +1 # size_counter 8 8 1 1 *4 # nb_inst_predict -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_mono_context.cfg
r81 r88 4 4 16 16 *4 # size_buffer 5 5 2 16 *4 # associativity 6 3 2 32*2 # size_address6 30 30 *2 # size_address 7 7 2 2 +1 # size_counter 8 8 1 4 *4 # nb_inst_predict -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_multi_context.cfg
r81 r88 7 7 8 64 *4 # size_buffer 8 8 4 8 *2 # associativity 9 3 2 32*2 # size_address9 30 30 *2 # size_address 10 10 2 2 +1 # size_counter 11 11 1 4 *4 # nb_inst_predict -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/main.cpp
r81 r88 67 67 _nb_inst_predict, 68 68 _nb_inst_decod , 69 _nb_inst_commit ); 69 _nb_inst_commit , 70 true // is_toplevel 71 ); 70 72 71 73 msg(_("%s"),param->print(1).c_str()); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp
r82 r88 14 14 #include "Common/include/BitManipulation.h" 15 15 #include "Behavioural/include/Allocation.h" 16 17 class entry_t 18 { 19 public : Tcontrol_t _val ; 20 public : Tcontext_t _context ; 21 public : Tcontrol_t _address_dest_val; 22 public : Tgeneral_data_t _address_src ; 23 public : Tgeneral_data_t _address_dest ; 24 public : Tbranch_condition_t _condition ; 25 public : Tcontrol_t _last_take ; 26 public : Tcounter_t _accurate ; 27 28 public : bool hit (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param, 29 Tgeneral_data_t addr_test, 30 Tcontext_t context) 31 { 32 Tgeneral_data_t addr_src_offset = (_address_src >> _param->_shift_offset)&_param->_mask_offset; 33 Tgeneral_data_t addr_src_index = (_address_src >> _param->_shift_bank )&_param->_mask_bank ; 34 Tgeneral_data_t addr_src_tag = (_address_src >> _param->_shift_tag ); 35 36 Tgeneral_data_t addr_test_offset = (addr_test >> _param->_shift_offset)&_param->_mask_offset; 37 Tgeneral_data_t addr_test_index = (addr_test >> _param->_shift_bank )&_param->_mask_bank ; 38 Tgeneral_data_t addr_test_tag = (addr_test >> _param->_shift_tag ); 39 40 bool is_hit = ( (_val == 1 ) and 41 (_context == context ) and 42 (addr_test_tag == addr_src_tag ) and 43 (addr_test_index == addr_src_index ) and 44 (addr_test_offset <= addr_src_offset )); 45 46 LABEL("address_src (tag, index, offset) : %.8x %.8x %.8x",addr_src_tag, addr_src_index, addr_src_offset); 47 LABEL("address_test (tag, index, offset) : %.8x %.8x %.8x - hit : %d",addr_test_tag, addr_test_index, addr_test_offset, is_hit); 48 return is_hit; 49 } 50 51 public : void print (void) 52 { 53 LABEL("%d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d", 54 _val , 55 _context , 56 _address_src , 57 _address_dest_val, 58 _address_dest , 59 _condition , 60 _last_take , 61 _accurate ); 62 63 } 64 65 }; 66 67 68 69 Tgeneral_data_t gen_addr (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param, 70 Tgeneral_data_t index) 71 { 72 Tgeneral_data_t addr_tag = (rand()%(2*_param->_associativity)) << _param->_shift_tag ; 73 Tgeneral_data_t addr_index = (index &_param->_mask_bank ) << _param->_shift_bank ; 74 Tgeneral_data_t addr_offset = (rand()&_param->_mask_offset ) << _param->_shift_offset; 75 76 LABEL("gen_addr (tag, index, offset) : %.8x %.8x %.8x",addr_tag, addr_index, addr_offset); 77 78 return (addr_tag | 79 addr_index | 80 addr_offset ); 81 } 82 16 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h" 83 17 84 18 void test (string name, … … 90 24 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); 91 25 #endif 26 27 Tusage_t _usage = USE_ALL; 28 29 // _usage = usage_unset(_usage,USE_SYSTEMC ); 30 // _usage = usage_unset(_usage,USE_VHDL ); 31 // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); 32 // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); 33 // _usage = usage_unset(_usage,USE_POSITION ); 34 // _usage = usage_unset(_usage,USE_STATISTICS ); 35 // _usage = usage_unset(_usage,USE_INFORMATION ); 92 36 93 37 Branch_Target_Buffer_Register * _Branch_Target_Buffer_Register = new Branch_Target_Buffer_Register … … 97 41 #endif 98 42 _param, 99 USE_ALL);43 _usage); 100 44 101 45 #ifdef SYSTEMC … … 269 213 in_DECOD_VICTIM [i]->write(rand()%_param->_associativity); 270 214 in_DECOD_CONTEXT_ID [i]->write(rand()%_param->_nb_context); 271 in_DECOD_ADDRESS_SRC [i]->write( addr);215 in_DECOD_ADDRESS_SRC [i]->write( addr); 272 216 in_DECOD_ADDRESS_DEST [i]->write(~addr); 273 217 in_DECOD_CONDITION [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK); … … 284 228 in_UPDATE_VICTIM [i]->write(rand()%_param->_associativity); 285 229 in_UPDATE_CONTEXT_ID [i]->write(rand()%_param->_nb_context); 286 in_UPDATE_ADDRESS_SRC [i]->write( addr);230 in_UPDATE_ADDRESS_SRC [i]->write( addr); 287 231 in_UPDATE_ADDRESS_DEST [i]->write(~addr); 288 232 in_UPDATE_CONDITION [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK); … … 334 278 335 279 bool hit = false; 336 337 for (uint32_t j=0; j<_param->_associativity; j++) 338 hit |= ((tab_old[j]._val == 1) and 339 (tab_old[j]._context == in_DECOD_CONTEXT_ID [i]->read()) and 340 (tab_old[j]._address_src == in_DECOD_ADDRESS_SRC [i]->read())); 280 281 Tptr_t k; 282 for (k=0; k<_param->_associativity; k++) 283 { 284 hit |= ((tab_old[k]._val == 1) and 285 (tab_old[k]._context == in_DECOD_CONTEXT_ID [i]->read()) and 286 (tab_old[k]._address_src == in_DECOD_ADDRESS_SRC [i]->read())); 287 288 if (hit) 289 break; 290 } 341 291 342 292 if (not hit) 343 293 { 344 Tptr_t k = in_DECOD_VICTIM [i]->read(); 345 294 k = in_DECOD_VICTIM [i]->read(); 346 295 LABEL(" * miss"); 347 296 LABEL(" * victim : %d",k); … … 354 303 tab[k]._condition = in_DECOD_CONDITION [i]->read(); 355 304 tab[k]._last_take = in_DECOD_LAST_TAKE [i]->read(); 356 //tab[k]._accurate = _param->_first_accurate_if_hit;305 tab[k]._accurate =(in_DECOD_IS_ACCURATE [i]->read())?_param->_first_accurate_if_hit:_param->_first_accurate_if_miss; 357 306 } 358 307 else 359 308 { 360 LABEL(" * miss"); 361 } 362 363 TEST(Tcontrol_t, out_DECOD_HIT [i]->read(), hit); 309 LABEL(" * hit"); 310 } 311 312 if (_param->_have_port_victim) 313 { 314 TEST(Tcontrol_t, out_DECOD_HIT [i]->read(), hit); 315 if (hit) 316 TEST(Tptr_t , out_DECOD_HIT_INDEX [i]->read(), k); 317 } 364 318 } 365 319 … … 373 327 bool hit = false; 374 328 375 Tptr_t k = 0;376 for ( uint32_t j=0; j<_param->_associativity; j++)377 { 378 hit |= ((tab_old[ j]._val == 1) and379 (tab_old[ j]._context == in_UPDATE_CONTEXT_ID [i]->read()) and380 (tab_old[ j]._address_src == in_UPDATE_ADDRESS_SRC [i]->read()));329 Tptr_t k; 330 for (k=0; k<_param->_associativity; k++) 331 { 332 hit |= ((tab_old[k]._val == 1) and 333 (tab_old[k]._context == in_UPDATE_CONTEXT_ID [i]->read()) and 334 (tab_old[k]._address_src == in_UPDATE_ADDRESS_SRC [i]->read())); 381 335 if (hit) 382 { 383 k = j; 384 break; 385 } 336 break; 386 337 } 387 338 … … 400 351 tab[k]._condition = in_UPDATE_CONDITION [i]->read(); 401 352 tab[k]._last_take = in_UPDATE_LAST_TAKE [i]->read(); 402 //tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;353 tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; 403 354 } 404 355 else … … 414 365 tab[k]._condition = in_UPDATE_CONDITION [i]->read(); 415 366 tab[k]._last_take = in_UPDATE_LAST_TAKE [i]->read(); 416 //tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; 417 } 418 419 TEST(Tcontrol_t, out_UPDATE_HIT [i]->read(), hit); 367 368 369 Tcounter_t accurate_old = tab[k]._accurate; 370 // hit : increase accurate 371 // miss : decrease accurate 372 Tcounter_t accurate_new = (in_UPDATE_MISS_PREDICTION [i]->read())?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old); 373 374 // test if accurate go to the threshold 375 if ((accurate_old >= _param->_accurate_limit) and 376 (accurate_new < _param->_accurate_limit)) 377 accurate_new = 0; 378 379 380 tab[k]._accurate = accurate_new; 381 } 382 383 if (_param->_have_port_victim) 384 { 385 TEST(Tcontrol_t, out_UPDATE_HIT [i]->read(), hit); 386 if (hit) 387 TEST(Tptr_t , out_UPDATE_HIT_INDEX [i]->read(), k); 388 } 420 389 } 421 390 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Parameters.h
r81 r88 31 31 public : uint32_t _size_buffer ; 32 32 public : uint32_t _associativity ; 33 33 //public : uint32_t _size_address ; 34 34 public : uint32_t _size_counter ; 35 35 public : uint32_t _nb_inst_predict; … … 38 38 39 39 public : uint32_t _size_bank ; 40 40 //public : uint32_t _size_context_id; 41 41 public : uint32_t _size_victim ; 42 42 43 43 //public : bool _have_port_context_id; 44 44 public : bool _have_port_victim ; 45 45 … … 65 65 uint32_t nb_inst_predict, 66 66 uint32_t nb_inst_decod , 67 uint32_t nb_inst_update ); 67 uint32_t nb_inst_update , 68 bool is_toplevel=false 69 ); 68 70 // public : Parameters (Parameters & param) ; 69 71 public : ~Parameters () ; 72 73 public : void copy (void); 70 74 71 75 public : Parameters_test msg_error (void); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp
r82 r88 39 39 log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); 40 40 41 #if DEBUG_Branch_Target_Buffer_Register == true 42 log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,_("<%s> Parameters"),_name.c_str()); 43 44 std::cout << *param << std::endl; 45 #endif 46 41 47 log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,"Allocation"); 42 48 … … 48 54 49 55 #ifdef STATISTICS 50 if ( _usage & USE_STATISTICS)56 if (usage_is_set(_usage,USE_STATISTICS)) 51 57 { 52 58 log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,"Allocation of statistics"); … … 57 63 58 64 #ifdef VHDL 59 if ( _usage & USE_VHDL)65 if (usage_is_set(_usage,USE_VHDL)) 60 66 { 61 67 // generate the vhdl … … 67 73 68 74 #ifdef SYSTEMC 69 if ( _usage & USE_SYSTEMC)75 if (usage_is_set(_usage,USE_SYSTEMC)) 70 76 { 71 77 // Constant … … 108 114 } 109 115 110 # ifdef SYSTEMCASS_SPECIFIC111 // List dependency information112 for (uint32_t i=0; i<_param->_nb_inst_predict; i++)113 for (uint32_t j=0; j<_param->_associativity; j++)114 {115 (*(out_PREDICT_HIT [i][j])) (*(in_PREDICT_ADDRESS [i]));116 if (_param->_have_port_context_id)117 (*(out_PREDICT_HIT [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));118 119 (*(out_PREDICT_ADDRESS_SRC [i][j])) (*(in_PREDICT_ADDRESS [i]));120 if (_param->_have_port_context_id)121 (*(out_PREDICT_ADDRESS_SRC [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));122 123 (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_ADDRESS [i]));124 if (_param->_have_port_context_id)125 (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));126 127 (*(out_PREDICT_CONDITION [i][j])) (*(in_PREDICT_ADDRESS [i]));128 if (_param->_have_port_context_id)129 (*(out_PREDICT_CONDITION [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));130 131 (*(out_PREDICT_LAST_TAKE [i][j])) (*(in_PREDICT_ADDRESS [i]));132 if (_param->_have_port_context_id)133 (*(out_PREDICT_LAST_TAKE [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));134 135 (*(out_PREDICT_IS_ACCURATE [i][j])) (*(in_PREDICT_ADDRESS [i]));136 if (_param->_have_port_context_id)137 (*(out_PREDICT_IS_ACCURATE [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));138 }139 # endif116 // # ifdef SYSTEMCASS_SPECIFIC 117 // // List dependency information 118 // for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 119 // for (uint32_t j=0; j<_param->_associativity; j++) 120 // { 121 // (*(out_PREDICT_HIT [i][j])) (*(in_PREDICT_ADDRESS [i])); 122 // if (_param->_have_port_context_id) 123 // (*(out_PREDICT_HIT [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); 124 125 // (*(out_PREDICT_ADDRESS_SRC [i][j])) (*(in_PREDICT_ADDRESS [i])); 126 // if (_param->_have_port_context_id) 127 // (*(out_PREDICT_ADDRESS_SRC [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); 128 129 // (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_ADDRESS [i])); 130 // if (_param->_have_port_context_id) 131 // (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); 132 133 // (*(out_PREDICT_CONDITION [i][j])) (*(in_PREDICT_ADDRESS [i])); 134 // if (_param->_have_port_context_id) 135 // (*(out_PREDICT_CONDITION [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); 136 137 // (*(out_PREDICT_LAST_TAKE [i][j])) (*(in_PREDICT_ADDRESS [i])); 138 // if (_param->_have_port_context_id) 139 // (*(out_PREDICT_LAST_TAKE [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); 140 141 // (*(out_PREDICT_IS_ACCURATE [i][j])) (*(in_PREDICT_ADDRESS [i])); 142 // if (_param->_have_port_context_id) 143 // (*(out_PREDICT_IS_ACCURATE [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); 144 // } 145 // # endif 140 146 141 147 if (_param->_have_port_victim) … … 215 221 216 222 #ifdef STATISTICS 217 if ( _usage & USE_STATISTICS)223 if (usage_is_set(_usage,USE_STATISTICS)) 218 224 { 219 225 statistics_deallocation(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp
r82 r88 64 64 ALLOC1_VALACK_OUT(out_PREDICT_ACK ,ACK); 65 65 ALLOC1_SIGNAL_IN ( in_PREDICT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 66 ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_ address);66 ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address); 67 67 68 68 { … … 70 70 71 71 ALLOC2_SIGNAL_OUT(out_PREDICT_HIT ,"hit" ,Tcontrol_t ,1); 72 ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_ address);73 ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_ address);72 ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); 73 ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_instruction_address); 74 74 ALLOC2_SIGNAL_OUT(out_PREDICT_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); 75 75 ALLOC2_SIGNAL_OUT(out_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); … … 91 91 } 92 92 ALLOC1_SIGNAL_IN ( in_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 93 ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_ address);94 ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_ address);93 ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); 94 ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address); 95 95 ALLOC1_SIGNAL_IN ( in_DECOD_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); 96 96 ALLOC1_SIGNAL_IN ( in_DECOD_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); … … 112 112 } 113 113 ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 114 ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_ address);115 ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_ address);114 ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); 115 ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address); 116 116 ALLOC1_SIGNAL_IN ( in_UPDATE_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); 117 117 ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); … … 119 119 } 120 120 121 if (usage_is_set(_usage,USE_SYSTEMC)) 122 { 121 123 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 122 124 reg_BTB = new btb_entry_t * [_param->_size_bank]; … … 133 135 internal_UPDATE_NUM_BANK = new uint32_t [_param->_nb_inst_update]; 134 136 internal_UPDATE_NUM_ENTRY = new uint32_t [_param->_nb_inst_update]; 137 } 135 138 136 139 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 137 140 138 141 #ifdef POSITION 139 _component->generate_file(); 142 if (usage_is_set(_usage,USE_POSITION)) 143 _component->generate_file(); 140 144 #endif 141 145 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp
r82 r88 24 24 log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); 25 25 26 if ( _usage & USE_SYSTEMC)26 if (usage_is_set(_usage,USE_SYSTEMC)) 27 27 { 28 28 delete in_CLOCK ; … … 42 42 delete [] in_DECOD_VAL ; 43 43 delete [] out_DECOD_ACK ; 44 if (_param->_have_port_victim) 45 { 44 46 delete [] out_DECOD_HIT ; 45 if (_param->_have_port_victim)46 47 delete [] out_DECOD_HIT_INDEX ; 47 if (_param->_have_port_victim)48 48 delete [] in_DECOD_VICTIM ; 49 } 49 50 if (_param->_have_port_context_id) 50 51 delete [] in_DECOD_CONTEXT_ID ; … … 57 58 delete [] in_UPDATE_VAL ; 58 59 delete [] out_UPDATE_ACK ; 60 if (_param->_have_port_victim) 61 { 59 62 delete [] out_UPDATE_HIT ; 60 if (_param->_have_port_victim)61 63 delete [] out_UPDATE_HIT_INDEX ; 62 if (_param->_have_port_victim)63 64 delete [] in_UPDATE_VICTIM ; 65 } 64 66 if (_param->_have_port_context_id) 65 67 delete [] in_UPDATE_CONTEXT_ID ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_end_cycle.cpp
r81 r88 26 26 27 27 #ifdef STATISTICS 28 _stat->end_cycle(); 28 if (usage_is_set(_usage,USE_STATISTICS)) 29 _stat->end_cycle(); 29 30 #endif 30 31 … … 32 33 // Evaluation before read the ouput signal 33 34 // sc_start(0); 34 _interfaces->testbench(); 35 if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) 36 _interfaces->testbench(); 35 37 #endif 36 38 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp
r82 r88 22 22 void Branch_Target_Buffer_Register::genMealy_decod (void) 23 23 { 24 log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); 24 log_begin(Branch_Target_Buffer_Register,FUNCTION); 25 log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str()); 25 26 26 27 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) … … 55 56 } 56 57 57 log_ printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");58 log_end(Branch_Target_Buffer_Register,FUNCTION); 58 59 }; 59 60 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp
r81 r88 22 22 void Branch_Target_Buffer_Register::genMealy_predict (void) 23 23 { 24 log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); 25 24 log_begin(Branch_Target_Buffer_Register,FUNCTION); 25 log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str()); 26 26 27 for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 27 28 { 29 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * PREDICT [%d]",i); 28 30 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; 29 31 Tgeneral_data_t address = PORT_READ(in_PREDICT_ADDRESS [i]); … … 33 35 Tgeneral_data_t address_offset = (address >> _param->_shift_offset)&_param->_mask_offset; 34 36 35 // log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"address_ (tag, bank, offset) : %.8x %.8x %.8x",address_tag,num_bank, address_offset);37 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * address_ (tag, bank, offset) : %.8x %.8x %.8x",address_tag,num_bank, address_offset); 36 38 37 39 for (uint32_t j=0; j<_param->_associativity; j++) … … 46 48 (address_src_offset >= address_offset)); 47 49 48 // log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"address_src (tag, bank, offset) : %.8x %.8x %.8x - hit : %d",address_src_tag,num_bank,address_src_offset, hit);50 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * address_src (tag, bank, offset) : %.8x %.8x %.8x - hit : %d",address_src_tag,num_bank,address_src_offset, hit); 49 51 50 52 // Hit : … … 62 64 } 63 65 64 log_ printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");66 log_end(Branch_Target_Buffer_Register,FUNCTION); 65 67 }; 66 68 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp
r82 r88 22 22 void Branch_Target_Buffer_Register::genMealy_update (void) 23 23 { 24 log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); 24 log_begin(Branch_Target_Buffer_Register,FUNCTION); 25 log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str()); 25 26 26 27 for (uint32_t i=0; i<_param->_nb_inst_update; i++) … … 55 56 } 56 57 57 log_ printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");58 log_end(Branch_Target_Buffer_Register,FUNCTION); 58 59 }; 59 60 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp
r82 r88 22 22 void Branch_Target_Buffer_Register::transition (void) 23 23 { 24 log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); 24 log_begin(Branch_Target_Buffer_Register,FUNCTION); 25 log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str()); 25 26 26 27 if (PORT_READ(in_NRESET) == 0) … … 83 84 if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) 84 85 { 86 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * UPDATE [%d]",i); 87 85 88 bool hit = internal_UPDATE_HIT [i]; 86 89 uint32_t num_bank = internal_UPDATE_NUM_BANK [i]; … … 89 92 90 93 // detect new branch !!! insert in branch target buffer 94 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * hit : %d",hit); 95 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_bank : %d",num_bank ); 96 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_entry : %d",num_entry); 97 91 98 Tcounter_t accurate_new = 0; 92 99 … … 123 130 accurate_new = (miss_pred)?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; 124 131 125 reg_BTB[num_bank][num_entry]._val = 1; 126 reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; 127 reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); 128 reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); 129 reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); 130 } 132 // reg_BTB[num_bank][num_entry]._val = 1; 133 // reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; 134 // reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); 135 // reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); 136 // reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); 137 reg_BTB[num_bank][num_entry]._address_dest_val = 0; 138 } 131 139 132 140 // =====[ All Case ] 133 if (reg_BTB[num_bank][num_entry]._address_dest_val == 0) 134 { 135 reg_BTB[num_bank][num_entry]._address_dest_val = 1; 136 reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); 137 } 141 // if (reg_BTB[num_bank][num_entry]._address_dest_val == 0) 142 // { 143 // reg_BTB[num_bank][num_entry]._address_dest_val = 1; 144 // reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); 145 // } 146 reg_BTB[num_bank][num_entry]._val = 1; 147 reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; 148 reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); 149 reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); 150 reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); 151 reg_BTB[num_bank][num_entry]._address_dest_val = 1; 152 reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); 138 153 reg_BTB[num_bank][num_entry]._accurate = accurate_new; 139 154 } 140 155 156 #if (DEBUG >= DEBUG_TRACE) and DEBUG_Branch_Target_Buffer_Register 157 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * Dump BTB"); 141 158 for (uint32_t i=0; i<_param->_size_bank; i++) 142 159 for (uint32_t j=0; j<_param->_associativity; j++) 143 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," [%.4d][%.4d] %d - %.2d %.8x %.1d %.8x%.3d %.1d %.4d",160 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," [%.4d][%.4d] %d - %.4d %.8x (%.8x) %.1d %.8x (%.8x) %.3d %.1d %.4d", 144 161 i,j, 145 162 reg_BTB [i][j]._val , 146 163 reg_BTB [i][j]._context , 147 164 reg_BTB [i][j]._address_src , 165 reg_BTB [i][j]._address_src <<2, 148 166 reg_BTB [i][j]._address_dest_val, 149 167 reg_BTB [i][j]._address_dest , 168 reg_BTB [i][j]._address_dest<<2 , 150 169 reg_BTB [i][j]._condition , 151 170 reg_BTB [i][j]._last_take , 152 171 reg_BTB [i][j]._accurate ); 172 #endif 153 173 } 154 174 155 175 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 156 176 end_cycle (); 157 177 #endif 158 178 159 log_ printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");179 log_end(Branch_Target_Buffer_Register,FUNCTION); 160 180 }; 161 181 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp
r81 r88 30 30 uint32_t nb_inst_predict, 31 31 uint32_t nb_inst_decod , 32 uint32_t nb_inst_update ) 32 uint32_t nb_inst_update , 33 bool is_toplevel) 33 34 { 34 35 log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); … … 38 39 _size_buffer = size_buffer ; 39 40 _associativity = associativity ; 40 _size_address = size_address ;41 41 _size_counter = size_counter ; 42 42 _nb_inst_predict = nb_inst_predict; … … 45 45 46 46 _size_bank = size_buffer/associativity; 47 _size_context_id = log2(nb_context);48 47 _size_victim = log2(associativity); 49 48 50 _have_port_context_id = (_size_context_id > 0);51 49 _have_port_victim = (_size_victim > 0); 52 50 … … 81 79 test(); 82 80 81 if (is_toplevel) 82 { 83 _size_instruction_address = size_address ; 84 _size_context_id = log2(nb_context); 85 _have_port_context_id = (_size_context_id > 0); 86 87 copy (); 88 } 89 83 90 log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); 84 91 }; … … 101 108 }; 102 109 110 #undef FUNCTION 111 #define FUNCTION "Branch_Target_Buffer_Register::copy" 112 void Parameters::copy () 113 { 114 log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); 115 log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); 116 }; 117 103 118 }; // end namespace branch_target_buffer_register 104 119 }; // end namespace branch_target_buffer -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_msg_error.cpp
r81 r88 29 29 30 30 if (_size_counter < 2 ) 31 test.error( "size_counter must be >= 2.");31 test.error(_("size_counter must be >= 2.\n")); 32 32 33 33 if ((_associativity == 0) or 34 34 (_associativity > _size_buffer)) 35 test.error( "associativity must be > 0 and <= size_buffer.");35 test.error(_("associativity must be > 0 and <= size_buffer.\n")); 36 36 37 37 if (_associativity == 1) // special case : full assoc and direct map ... also we print direct map 38 test.information( "Branch Target Buffer is Direct Map");38 test.information(_("Branch Target Buffer is Direct Map.\n")); 39 39 else 40 40 if (_associativity == _size_buffer) 41 test.information( "Branch Target Buffer is Full associative");41 test.information(_("Branch Target Buffer is Full associative.\n")); 42 42 else 43 test.information( "Branch Target Buffer is Semi associative");43 test.information(_("Branch Target Buffer is Semi associative.\n")); 44 44 45 45 for (uint32_t i=0; i<_nb_context; i++) 46 46 if (_associativity < (_nb_instruction[i]/2)) 47 test.error( "associativity must be >= nb_instruction["+toString(i)+"]/2.");47 test.error(toString(_("associativity must be >= nb_instruction[%d]/2.\n"),i)); 48 48 49 49 log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_print.cpp
r81 r88 31 31 xml.singleton_begin("size_buffer "); xml.attribut("value",toString(_size_buffer )); xml.singleton_end(); 32 32 xml.singleton_begin("associativity "); xml.attribut("value",toString(_associativity )); xml.singleton_end(); 33 33 // xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); 34 34 xml.singleton_begin("size_counter "); xml.attribut("value",toString(_size_counter )); xml.singleton_end(); 35 35 xml.singleton_begin("nb_inst_predict"); xml.attribut("value",toString(_nb_inst_predict)); xml.singleton_end();
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