Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (16 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp
r82 r88 14 14 #include "Common/include/BitManipulation.h" 15 15 #include "Behavioural/include/Allocation.h" 16 17 class entry_t 18 { 19 public : Tcontrol_t _val ; 20 public : Tcontext_t _context ; 21 public : Tcontrol_t _address_dest_val; 22 public : Tgeneral_data_t _address_src ; 23 public : Tgeneral_data_t _address_dest ; 24 public : Tbranch_condition_t _condition ; 25 public : Tcontrol_t _last_take ; 26 public : Tcounter_t _accurate ; 27 28 public : bool hit (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param, 29 Tgeneral_data_t addr_test, 30 Tcontext_t context) 31 { 32 Tgeneral_data_t addr_src_offset = (_address_src >> _param->_shift_offset)&_param->_mask_offset; 33 Tgeneral_data_t addr_src_index = (_address_src >> _param->_shift_bank )&_param->_mask_bank ; 34 Tgeneral_data_t addr_src_tag = (_address_src >> _param->_shift_tag ); 35 36 Tgeneral_data_t addr_test_offset = (addr_test >> _param->_shift_offset)&_param->_mask_offset; 37 Tgeneral_data_t addr_test_index = (addr_test >> _param->_shift_bank )&_param->_mask_bank ; 38 Tgeneral_data_t addr_test_tag = (addr_test >> _param->_shift_tag ); 39 40 bool is_hit = ( (_val == 1 ) and 41 (_context == context ) and 42 (addr_test_tag == addr_src_tag ) and 43 (addr_test_index == addr_src_index ) and 44 (addr_test_offset <= addr_src_offset )); 45 46 LABEL("address_src (tag, index, offset) : %.8x %.8x %.8x",addr_src_tag, addr_src_index, addr_src_offset); 47 LABEL("address_test (tag, index, offset) : %.8x %.8x %.8x - hit : %d",addr_test_tag, addr_test_index, addr_test_offset, is_hit); 48 return is_hit; 49 } 50 51 public : void print (void) 52 { 53 LABEL("%d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d", 54 _val , 55 _context , 56 _address_src , 57 _address_dest_val, 58 _address_dest , 59 _condition , 60 _last_take , 61 _accurate ); 62 63 } 64 65 }; 66 67 68 69 Tgeneral_data_t gen_addr (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param, 70 Tgeneral_data_t index) 71 { 72 Tgeneral_data_t addr_tag = (rand()%(2*_param->_associativity)) << _param->_shift_tag ; 73 Tgeneral_data_t addr_index = (index &_param->_mask_bank ) << _param->_shift_bank ; 74 Tgeneral_data_t addr_offset = (rand()&_param->_mask_offset ) << _param->_shift_offset; 75 76 LABEL("gen_addr (tag, index, offset) : %.8x %.8x %.8x",addr_tag, addr_index, addr_offset); 77 78 return (addr_tag | 79 addr_index | 80 addr_offset ); 81 } 82 16 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h" 83 17 84 18 void test (string name, … … 90 24 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); 91 25 #endif 26 27 Tusage_t _usage = USE_ALL; 28 29 // _usage = usage_unset(_usage,USE_SYSTEMC ); 30 // _usage = usage_unset(_usage,USE_VHDL ); 31 // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); 32 // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); 33 // _usage = usage_unset(_usage,USE_POSITION ); 34 // _usage = usage_unset(_usage,USE_STATISTICS ); 35 // _usage = usage_unset(_usage,USE_INFORMATION ); 92 36 93 37 Branch_Target_Buffer_Register * _Branch_Target_Buffer_Register = new Branch_Target_Buffer_Register … … 97 41 #endif 98 42 _param, 99 USE_ALL);43 _usage); 100 44 101 45 #ifdef SYSTEMC … … 269 213 in_DECOD_VICTIM [i]->write(rand()%_param->_associativity); 270 214 in_DECOD_CONTEXT_ID [i]->write(rand()%_param->_nb_context); 271 in_DECOD_ADDRESS_SRC [i]->write( addr);215 in_DECOD_ADDRESS_SRC [i]->write( addr); 272 216 in_DECOD_ADDRESS_DEST [i]->write(~addr); 273 217 in_DECOD_CONDITION [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK); … … 284 228 in_UPDATE_VICTIM [i]->write(rand()%_param->_associativity); 285 229 in_UPDATE_CONTEXT_ID [i]->write(rand()%_param->_nb_context); 286 in_UPDATE_ADDRESS_SRC [i]->write( addr);230 in_UPDATE_ADDRESS_SRC [i]->write( addr); 287 231 in_UPDATE_ADDRESS_DEST [i]->write(~addr); 288 232 in_UPDATE_CONDITION [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK); … … 334 278 335 279 bool hit = false; 336 337 for (uint32_t j=0; j<_param->_associativity; j++) 338 hit |= ((tab_old[j]._val == 1) and 339 (tab_old[j]._context == in_DECOD_CONTEXT_ID [i]->read()) and 340 (tab_old[j]._address_src == in_DECOD_ADDRESS_SRC [i]->read())); 280 281 Tptr_t k; 282 for (k=0; k<_param->_associativity; k++) 283 { 284 hit |= ((tab_old[k]._val == 1) and 285 (tab_old[k]._context == in_DECOD_CONTEXT_ID [i]->read()) and 286 (tab_old[k]._address_src == in_DECOD_ADDRESS_SRC [i]->read())); 287 288 if (hit) 289 break; 290 } 341 291 342 292 if (not hit) 343 293 { 344 Tptr_t k = in_DECOD_VICTIM [i]->read(); 345 294 k = in_DECOD_VICTIM [i]->read(); 346 295 LABEL(" * miss"); 347 296 LABEL(" * victim : %d",k); … … 354 303 tab[k]._condition = in_DECOD_CONDITION [i]->read(); 355 304 tab[k]._last_take = in_DECOD_LAST_TAKE [i]->read(); 356 //tab[k]._accurate = _param->_first_accurate_if_hit;305 tab[k]._accurate =(in_DECOD_IS_ACCURATE [i]->read())?_param->_first_accurate_if_hit:_param->_first_accurate_if_miss; 357 306 } 358 307 else 359 308 { 360 LABEL(" * miss"); 361 } 362 363 TEST(Tcontrol_t, out_DECOD_HIT [i]->read(), hit); 309 LABEL(" * hit"); 310 } 311 312 if (_param->_have_port_victim) 313 { 314 TEST(Tcontrol_t, out_DECOD_HIT [i]->read(), hit); 315 if (hit) 316 TEST(Tptr_t , out_DECOD_HIT_INDEX [i]->read(), k); 317 } 364 318 } 365 319 … … 373 327 bool hit = false; 374 328 375 Tptr_t k = 0;376 for ( uint32_t j=0; j<_param->_associativity; j++)377 { 378 hit |= ((tab_old[ j]._val == 1) and379 (tab_old[ j]._context == in_UPDATE_CONTEXT_ID [i]->read()) and380 (tab_old[ j]._address_src == in_UPDATE_ADDRESS_SRC [i]->read()));329 Tptr_t k; 330 for (k=0; k<_param->_associativity; k++) 331 { 332 hit |= ((tab_old[k]._val == 1) and 333 (tab_old[k]._context == in_UPDATE_CONTEXT_ID [i]->read()) and 334 (tab_old[k]._address_src == in_UPDATE_ADDRESS_SRC [i]->read())); 381 335 if (hit) 382 { 383 k = j; 384 break; 385 } 336 break; 386 337 } 387 338 … … 400 351 tab[k]._condition = in_UPDATE_CONDITION [i]->read(); 401 352 tab[k]._last_take = in_UPDATE_LAST_TAKE [i]->read(); 402 //tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;353 tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; 403 354 } 404 355 else … … 414 365 tab[k]._condition = in_UPDATE_CONDITION [i]->read(); 415 366 tab[k]._last_take = in_UPDATE_LAST_TAKE [i]->read(); 416 //tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; 417 } 418 419 TEST(Tcontrol_t, out_UPDATE_HIT [i]->read(), hit); 367 368 369 Tcounter_t accurate_old = tab[k]._accurate; 370 // hit : increase accurate 371 // miss : decrease accurate 372 Tcounter_t accurate_new = (in_UPDATE_MISS_PREDICTION [i]->read())?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old); 373 374 // test if accurate go to the threshold 375 if ((accurate_old >= _param->_accurate_limit) and 376 (accurate_new < _param->_accurate_limit)) 377 accurate_new = 0; 378 379 380 tab[k]._accurate = accurate_new; 381 } 382 383 if (_param->_have_port_victim) 384 { 385 TEST(Tcontrol_t, out_UPDATE_HIT [i]->read(), hit); 386 if (hit) 387 TEST(Tptr_t , out_UPDATE_HIT_INDEX [i]->read(), k); 388 } 420 389 } 421 390
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