Changeset 94 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
- Timestamp:
- Dec 15, 2008, 12:04:03 PM (16 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r88 r94 45 45 reg_UPT_TOP [i] = 0; 46 46 reg_UPT_UPDATE [i] = 0; 47 reg_UPT_NB_NEED_UPDATE [i] = 0;48 47 49 48 reg_IS_ACCURATE [i] = true; 50 49 51 50 reg_EVENT_STATE [i] = EVENT_STATE_OK; 52 51 } … … 54 53 else 55 54 { 55 bool flush_UFPT [_param->_nb_context]; 56 for (uint32_t i=0; i<_param->_nb_context; i++) 57 flush_UFPT [i] = false; 58 56 59 // =================================================================== 57 60 // =====[ GARBAGE COLLECTOR ]========================================= … … 166 169 Tbranch_condition_t condition ; 167 170 Tcontrol_t is_accurate; 171 Taddress_t address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]); 172 Taddress_t address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]); 173 Tcontrol_t last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]); 168 174 169 175 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i); … … 176 182 { 177 183 // Have a miss !!! 184 #ifdef DEBUG_TEST 185 if (reg_EVENT_STATE [context] != EVENT_STATE_OK) 186 throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); 187 #endif 188 189 if (reg_UFPT_NB_NEED_UPDATE [context] == 0) 190 { 191 // Change state 192 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context); 193 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 194 } 195 else 196 { 197 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT (decod - miss - flush ufpt)",context); 198 reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT; 199 } 178 200 179 201 // Flush UPFT 180 181 // It's to accelerate miss speculation 182 if (reg_UFPT_NB_NEED_UPDATE [context] == 0) 183 { 184 // No entry need prediction, flush all entry -> Reset 185 for (uint32_t j=0; j<_param->_size_ufpt_queue[context]; ++j) 186 reg_UPDATE_FETCH_PREDICTION_TABLE [context][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; 187 reg_UFPT_BOTTOM [context] = 0; 188 reg_UFPT_TOP [context] = 0; 189 // reg_UFPT_UPDATE [context] = 0; 190 } 191 else 192 { 193 reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context]; 194 195 #ifdef DEBUG_TEST 196 if (reg_EVENT_STATE [context] == EVENT_STATE_OK) 197 throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); 198 #endif 199 200 // Change state 201 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT (decod - miss)",context); 202 203 reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT; 204 } 202 flush_UFPT [context] = true; 203 204 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State 205 reg_EVENT_ADDRESS_DEST_VAL[context] = last_take; 206 reg_EVENT_ADDRESS_DEST [context] = address_dest; 205 207 206 208 // Push upt (from decod interface) … … 209 211 210 212 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition; 211 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]);212 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);213 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]);213 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = address_src ; 214 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = address_dest; 215 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = last_take ; 214 216 // reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take; 215 217 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate; … … 277 279 reg_UPT_TOP [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context]; 278 280 // reg_UPT_UPDATE [context] = reg_UPT_TOP [context]; 279 if (need_update(condition))280 {281 reg_UPT_NB_NEED_UPDATE [context] ++;282 }283 281 } 284 282 … … 296 294 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 297 295 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 296 Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i]; 297 Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i]; 298 Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; 298 299 299 300 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); 300 301 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 301 302 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 302 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d", internal_BRANCH_COMPLETE_MISS_PREDICTION [i]);303 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 303 304 304 if (internal_BRANCH_COMPLETE_MISS_PREDICTION [i])305 if (miss) 305 306 { 306 // Miss case 307 // // breakpoint("Branch_complete and miss ..."); 308 309 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_EVENT (branch_complete)",context,depth); 310 // reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 311 312 // // Another prediction (prediction with depth higer) 313 // Tdepth_t top = reg_TOP[context];314 // uint32_t nb_elt_miss = ((top> depth)?top:(top+_param->_size_queue[context]))-depth; 315 // uint32_t nb_elt_need_update = 1; 316 // for (uint32_t j=1; j<nb_elt_miss; j++) 317 // { 318 // uint32_t k=(depth+j)%_param->_size_queue[context]; 319 320 // // Ifetch have make a prediction and it's a miss 321 // // When ifetch predict :322 // // * btb is not change -> needn't update 323 // // * direction is not change -> needn't update 324 // // * ras have change -> need update 325 326 // Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][k]._condition;327 // if ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or 328 // (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or 329 // (cond == BRANCH_CONDITION_READ_STACK)) 330 // { 331 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch miss, update ras)",context,k); 332 333 // nb_elt_need_update ++;334 // reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_KO; 335 // } 336 // else 337 // { 338 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_END (branch_complete, ifetch miss, don't update ras)",context,k);339 340 // reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_END; 341 // } 342 // } 343 // reg_NB_ELT_NEED_UPDATE [context] += nb_elt_need_update; 344 345 // // Update pointer : 346 // reg_TOP [context] = depth; 347 // reg_NB_ELT [context] -= nb_elt_miss; 348 // reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];349 307 // Have a miss !!! 308 // Flush UPFT 309 flush_UFPT [context] = true; 310 311 // Flush UPT 312 uint32_t top = reg_UPT_TOP [context]; 313 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 314 for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; 315 j!=top; 316 j=(j+1)%_param->_size_upt_queue[context]) 317 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; 318 319 // TOP is next write slot : last slot is TOP-1 320 reg_UPT_UPDATE [context] = new_update; 321 322 // reg_UPT_BOTTOM [context]; 323 reg_UPT_TOP [context] = depth; 324 325 #ifdef DEBUG_TEST 326 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 327 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 328 #endif 329 330 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); 331 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; 332 333 334 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; 335 336 if (reg_UFPT_NB_NEED_UPDATE [context] > 0) 337 { 338 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); 339 reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT_AND_UPT; 340 } 341 else 342 { 343 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT_RAS (branch_complete - miss)",context); 344 // have ras prediction ? 345 reg_EVENT_STATE [context] = (new_update!=depth)?EVENT_STATE_FLUSH_UPT_RAS:EVENT_STATE_UPDATE_CONTEXT; 346 } 347 348 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State 349 reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; 350 reg_EVENT_ADDRESS_DEST [context] = good_addr; 350 351 } 351 352 else … … 363 364 364 365 // In all case : update good_take 365 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = internal_BRANCH_COMPLETE_TAKE [i];366 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; 366 367 } 367 368 … … 381 382 if (internal_UPDATE_FROM_UFPT [i]) 382 383 { 384 // if free a slot, also all queue is updated 385 // Last slot ? 386 if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) 387 switch (reg_EVENT_STATE [context]) 388 { 389 case EVENT_STATE_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break; 390 case EVENT_STATE_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = (reg_UPT_UPDATE[context]!=reg_UPT_TOP[context])?EVENT_STATE_FLUSH_UPT_RAS:EVENT_STATE_UPDATE_CONTEXT; break; 391 default : break; 392 } 393 383 394 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); 384 395 … … 393 404 reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END; 394 405 406 395 407 // Update pointer 396 reg_UFPT_UPDATE [context] = (depth==0)?(_param->_size_ufpt_queue[context]-1):(depth-1); 397 408 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]); 409 reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1; 410 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]); 398 411 // Free a register that need update ? 399 412 if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition)) … … 405 418 406 419 // Change state 407 #ifdef DEBUG_TEST 408 if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK ) and 409 (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) and 410 (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT)) 411 throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); 420 #ifdef DEBUG_TEST 421 if (internal_UPDATE_RAS [i]) 422 { 423 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) 424 throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); 425 } 426 else 427 { 428 if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK ) and 429 (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO )) 430 throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); 431 } 412 432 #endif 413 433 … … 417 437 418 438 // Update pointer 439 bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]); 440 419 441 if (internal_UPDATE_RAS [i]) 420 reg_UPT_UPDATE [context] = (depth==0)?(_param->_size_upt_queue[context]-1):(depth-1); 442 { 443 reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1); 444 } 421 445 else 422 reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; 423 424 // Free a register that need update ? 425 if (need_update(reg_UPDATE_PREDICTION_TABLE [context][depth]._condition)) 426 reg_UPT_NB_NEED_UPDATE [context] --; 446 { 447 reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; 448 } 449 450 // End and event ? 451 if (end_event and 452 (reg_EVENT_STATE [context] != EVENT_STATE_OK)) 453 { 454 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 455 } 456 427 457 // Free the branch with no accurate ? 428 458 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) 429 reg_IS_ACCURATE [ i] = true;459 reg_IS_ACCURATE [context] = true; 430 460 } 431 461 } … … 434 464 reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; 435 465 436 // // =================================================================== 437 // // =====[ BRANCH_EVENT ]============================================== 438 // // =================================================================== 439 // for (uint32_t i=0; i<_param->_nb_context; i++) 440 // if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i])) 441 // { 442 // Tdepth_t depth = internal_BRANCH_EVENT_DEPTH [i]; 443 444 // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_EVENT) 445 // { 446 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_KO (branch_event)",i,depth); 447 448 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_KO; 449 // } 450 // else 451 // { 452 // #ifdef DEBUG_TEST 453 // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_WAITEND_AND_EVENT) 454 // throw ERRORMORPHEO(FUNCTION,_("Branche event : invalid state")); 455 // #endif 456 457 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_WAITEND (branch_event)",i,depth); 458 459 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_WAITEND; 460 // } 461 // } 466 // =================================================================== 467 // =====[ BRANCH_EVENT ]============================================== 468 // =================================================================== 469 for (uint32_t i=0; i<_param->_nb_context; i++) 470 if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i])) 471 { 472 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); 473 474 #ifdef DEBUG_TEST 475 if (reg_EVENT_STATE [i] != EVENT_STATE_UPDATE_CONTEXT) 476 throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); 477 #endif 478 479 // Change state 480 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (branch_event)",i); 481 482 reg_EVENT_STATE [i] = EVENT_STATE_OK; 483 } 484 485 // =================================================================== 486 // =====[ FLUSH ]===================================================== 487 // =================================================================== 488 489 for (uint32_t i=0; i<_param->_nb_context; ++i) 490 { 491 if (flush_UFPT [i]) 492 { 493 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Flush Update Fetch Prediction Table"); 494 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i); 495 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); 496 497 // It's to accelerate miss speculation 498 if (reg_UFPT_NB_NEED_UPDATE [i] == 0) 499 { 500 501 // No entry need prediction, flush all entry -> Reset 502 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) 503 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; 504 reg_UFPT_BOTTOM [i] = 0; 505 reg_UFPT_TOP [i] = 0; 506 // reg_UFPT_UPDATE [i]; 507 } 508 else 509 { 510 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) 511 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; 512 513 // TOP is next write slot : last slot is TOP-1 514 uint32_t top = reg_UFPT_TOP [i]; 515 reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1; 516 517 // reg_UFPT_BOTTOM [i]; 518 // reg_UFPT_TOP [i]; 519 } 520 521 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [i]); 522 523 } 524 } 525 526 // =================================================================== 527 // =====[ PRINT ]===================================================== 528 // =================================================================== 462 529 463 530 #if (DEBUG >= DEBUG_TRACE) … … 468 535 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]); 469 536 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); 470 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_RAS_CORRUPTED : %d" ,reg_EVENT_RAS_CORRUPTED [i]);471 537 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x",reg_EVENT_ADDRESS_SRC [i]); 472 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_ SRC_VAL : %d" ,reg_EVENT_ADDRESS_SRC_VAL[i]);538 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]); 473 539 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x",reg_EVENT_ADDRESS_DEST [i]); 474 540 … … 476 542 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]); 477 543 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]); 544 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]); 478 545 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); 479 546 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) … … 495 562 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); 496 563 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); 497 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_NB_NEED_UPDATE : %d",reg_UPT_NB_NEED_UPDATE [i]);498 564 for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) 499 565 log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d %.1d, %.8d %.8x %.4d - %s",
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