Changeset 97 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include

Timestamp:

Dec 19, 2008, 4:34:00 PM (16 years ago)

Author:

rosiere

Message:

1) Update Prediction Table : statistics
2) Size instruction address on 30 bits
3) Change Log File
4) Add debug_level in simulation configuration file

Location:

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include

Files:

• Types.h (modified) (3 diffs)
• Write_queue.h (modified) (3 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Types.h

@@ -27 +27 @@
   public  : Tpacket_t          _packet_id    ;
 //public  : Toperation_t       _operation    ;
-  public  : Ttype_t            _type         ;
+//public  : Ttype_t            _type         ;
   public  : Tcontrol_t         _write_rd     ;
   public  : Tgeneral_address_t _num_reg_rd   ;
@@ -42 +42 @@
                                  Tcontext_t         ooo_engine_id,
                                  Tpacket_t          packet_id    ,
-                               //Toperation_t       operation    ,
-                                 Ttype_t            type         ,
+//                               Toperation_t       operation    ,
+//                               Ttype_t            type         ,
                                  Tcontrol_t         write_rd     ,
                                  Tgeneral_address_t num_reg_rd   ,
@@ -59 +59 @@
       _packet_id     = packet_id    ;
     //_operation     = operation    ;
-      _type          = type         ;
+    //_type          = type         ;
       _write_rd      = write_rd     ;
       _num_reg_rd    = num_reg_rd   ;

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h

@@ -76 +76 @@
   public    : SC_IN (Tpacket_t         )    *  in_WRITE_QUEUE_IN_PACKET_ID    ;
 //public    : SC_IN (Toperation_t      )    *  in_WRITE_QUEUE_IN_OPERATION    ;
-  public    : SC_IN (Ttype_t           )    *  in_WRITE_QUEUE_IN_TYPE         ;
+//public    : SC_IN (Ttype_t           )    *  in_WRITE_QUEUE_IN_TYPE         ;
   public    : SC_IN (Tcontrol_t        )    *  in_WRITE_QUEUE_IN_WRITE_RD     ;
   public    : SC_IN (Tgeneral_address_t)    *  in_WRITE_QUEUE_IN_NUM_REG_RD   ;
@@ -85 +85 @@
   public    : SC_IN (Texception_t      )    *  in_WRITE_QUEUE_IN_EXCEPTION    ;
   public    : SC_IN (Tcontrol_t        )    *  in_WRITE_QUEUE_IN_NO_SEQUENCE  ;
-  public    : SC_IN (Tgeneral_data_t   )    *  in_WRITE_QUEUE_IN_ADDRESS      ;
+  public    : SC_IN (Taddress_t        )    *  in_WRITE_QUEUE_IN_ADDRESS      ;
 
     // -----[ Interface "Write_queue_out" ]-------------------------------    
@@ -99 +99 @@
   public    : SC_OUT(Texception_t      )    * out_WRITE_QUEUE_OUT_EXCEPTION    ;
   public    : SC_OUT(Tcontrol_t        )    * out_WRITE_QUEUE_OUT_NO_SEQUENCE  ;
-  public    : SC_OUT(Tgeneral_data_t   )    * out_WRITE_QUEUE_OUT_ADDRESS      ;
+  public    : SC_OUT(Taddress_t        )    * out_WRITE_QUEUE_OUT_ADDRESS      ;
   public    : SC_OUT(Tgeneral_data_t   )    * out_WRITE_QUEUE_OUT_DATA         ;