Ignore:
Timestamp:
Dec 19, 2008, 4:34:00 PM (16 years ago)
Author:
rosiere
Message:

1) Update Prediction Table : statistics
2) Size instruction address on 30 bits
3) Change Log File
4) Add debug_level in simulation configuration file

File:
1 edited

Legend:

Unmodified
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Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h

    r88 r97  
    7676  public    : SC_IN (Tpacket_t         )    *  in_WRITE_QUEUE_IN_PACKET_ID    ;
    7777//public    : SC_IN (Toperation_t      )    *  in_WRITE_QUEUE_IN_OPERATION    ;
    78   public    : SC_IN (Ttype_t           )    *  in_WRITE_QUEUE_IN_TYPE         ;
     78//public    : SC_IN (Ttype_t           )    *  in_WRITE_QUEUE_IN_TYPE         ;
    7979  public    : SC_IN (Tcontrol_t        )    *  in_WRITE_QUEUE_IN_WRITE_RD     ;
    8080  public    : SC_IN (Tgeneral_address_t)    *  in_WRITE_QUEUE_IN_NUM_REG_RD   ;
    … …  
    8585  public    : SC_IN (Texception_t      )    *  in_WRITE_QUEUE_IN_EXCEPTION    ;
    8686  public    : SC_IN (Tcontrol_t        )    *  in_WRITE_QUEUE_IN_NO_SEQUENCE  ;
    87   public    : SC_IN (Tgeneral_data_t   )    *  in_WRITE_QUEUE_IN_ADDRESS      ;
     87  public    : SC_IN (Taddress_t        )    *  in_WRITE_QUEUE_IN_ADDRESS      ;
    8888
    8989    // -----[ Interface "Write_queue_out" ]-------------------------------   
    … …  
    9999  public    : SC_OUT(Texception_t      )    * out_WRITE_QUEUE_OUT_EXCEPTION    ;
    100100  public    : SC_OUT(Tcontrol_t        )    * out_WRITE_QUEUE_OUT_NO_SEQUENCE  ;
    101   public    : SC_OUT(Tgeneral_data_t   )    * out_WRITE_QUEUE_OUT_ADDRESS      ;
     101  public    : SC_OUT(Taddress_t        )    * out_WRITE_QUEUE_OUT_ADDRESS      ;
    102102  public    : SC_OUT(Tgeneral_data_t   )    * out_WRITE_QUEUE_OUT_DATA         ;
    103103
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