Changeset 97 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp

Timestamp:

Dec 19, 2008, 4:34:00 PM (16 years ago)

Author:

rosiere

Message:

1) Update Prediction Table : statistics
2) Size instruction address on 30 bits
3) Change Log File
4) Add debug_level in simulation configuration file

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp (modified) (1 diff)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp

@@ -84 +84 @@
   ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_EXCEPTION           ,"out_EXECUTE_LOOP_OUT_EXCEPTION           ",Texception_t      ,_param->_nb_write_unit);
   ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_NO_SEQUENCE         ,"out_EXECUTE_LOOP_OUT_NO_SEQUENCE         ",Tcontrol_t        ,_param->_nb_write_unit);
-  ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_ADDRESS             ,"out_EXECUTE_LOOP_OUT_ADDRESS             ",Tgeneral_data_t   ,_param->_nb_write_unit);
+  ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_ADDRESS             ,"out_EXECUTE_LOOP_OUT_ADDRESS             ",Taddress_t        ,_param->_nb_write_unit);
   ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_DATA                ,"out_EXECUTE_LOOP_OUT_DATA                ",Tgeneral_data_t   ,_param->_nb_write_unit);
   ALLOC2_SC_SIGNAL(out_DCACHE_REQ_VAL                       ,"out_DCACHE_REQ_VAL                       ",Tcontrol_t        ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]);