Ignore:
Timestamp:
Dec 19, 2008, 4:34:00 PM (16 years ago)
Author:
rosiere
Message:

1) Update Prediction Table : statistics
2) Size instruction address on 30 bits
3) Change Log File
4) Add debug_level in simulation configuration file

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp

    r88 r97  
    3838        // SR can't change in this cycle
    3939        // Exception Prefix High
    40         Taddress_t address          = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);
    41         Taddress_t address_next     = reg_EVENT_ADDRESS_EPCR [i];
    42         Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
    43         Tcontrol_t is_ds_take       = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]);
     40        Taddress_t    address          = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);
     41        Taddress_t    address_next     = reg_EVENT_ADDRESS_EPCR [i];
     42        Tcontrol_t    address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
     43        Tcontrol_t    is_ds_take       = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]);
    4444        // excep : address exception
    4545        // miss  : address delay_slot, and address dest
    4646        // psync : address next
    4747        // csync : address next
     48        Tevent_type_t type                         ;//[nb_context]
     49        Tdepth_t      depth            = reg_EVENT_DEPTH [i];
     50
     51        switch (state)
     52          {
     53          case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION         ); break;
     54          case CONTEXT_STATE_KO_MISS_ADDR  : (type = EVENT_TYPE_MISS_SPECULATION  ); break;
     55          case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC             ); break;
     56          case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC             ); break;
     57          default                          : (type = EVENT_TYPE_NONE              ); break;
     58          }
     59//      (type = EVENT_TYPE_SPR_ACCESS        );
     60//      (type = EVENT_TYPE_MSYNC             );
     61//      (type = EVENT_TYPE_BRANCH_NO_ACCURATE);
     62
    4863        internal_EVENT_VAL [i] = val;
    4964        PORT_WRITE(out_EVENT_VAL              [i], val);
    … …  
    5267        PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val);
    5368        PORT_WRITE(out_EVENT_IS_DS_TAKE       [i], is_ds_take);
     69        PORT_WRITE(out_EVENT_TYPE             [i], type);
     70        if (_param->_have_port_depth)
     71        PORT_WRITE(out_EVENT_DEPTH            [i], depth);
    5472
    5573        log_printf(TRACE,Context_State,FUNCTION,"  * EVENT Context      : %d", i);
    … …  
    5977        log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS_NEXT_VAL : %d", address_next_val);
    6078        log_printf(TRACE,Context_State,FUNCTION,"    * IS_DS_TAKE       : %d", is_ds_take);
     79        log_printf(TRACE,Context_State,FUNCTION,"    * TYPE             : %d", type);
     80        log_printf(TRACE,Context_State,FUNCTION,"    * DEPTH            : %d", depth);
    6181      }
    6282
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