Changeset 98 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp

Timestamp:

Dec 31, 2008, 11:18:08 AM (16 years ago)

Author:

rosiere

Message:

1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...)
2) Change VHDL Execute_queue -> use Generic/Queue?
3) Complete document on VHDL generation
4) Add soc test

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp (modified) (8 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp

@@ -55 +55 @@
   ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_DEPTH           ,"out_BRANCH_COMPLETE_FRONT_END_DEPTH           ",Tdepth_t          ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
   ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ADDRESS         ,"out_BRANCH_COMPLETE_FRONT_END_ADDRESS         ",Taddress_t        ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
-  ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_FLAG            ,"out_BRANCH_COMPLETE_FRONT_END_FLAG            ",Tcontrol_t        ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
+  ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE     ,"out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE     ",Tcontrol_t        ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
   ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ," in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ",Tcontrol_t        ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
   ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_VAL            ," in_BRANCH_COMPLETE_OOO_ENGINE_VAL            ",Tcontrol_t        ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
@@ -63 +63 @@
   ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH          ," in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH          ",Tdepth_t          ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
   ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS        ," in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS        ",Taddress_t        ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
-  ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_FLAG           ," in_BRANCH_COMPLETE_OOO_ENGINE_FLAG           ",Tcontrol_t        ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
+  ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE    ," in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE    ",Tcontrol_t        ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
   ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,"out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION",Tcontrol_t        ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
   ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_VAL                ,"out_COMMIT_EVENT_FRONT_END_VAL                ",Tcontrol_t        ,_param->_nb_front_end);
@@ -186 +186 @@
   INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_DEPTH           ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
   INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_ADDRESS         ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
-  INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_FLAG            ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
+  INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE     ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
   INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
   INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_VAL            ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
@@ -197 +197 @@
   INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH          ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
   INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS        ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
-  INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_FLAG           ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
+  INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE    ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
   INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
   INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_VAL                ,_param->_nb_front_end);
@@ -393 +393 @@
             in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH        [i][j]->write(range<Tdepth_t  >(rand(),_param->_size_depth              ));
             in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS      [i][j]->write(range<Taddress_t>(rand(),_param->_size_instruction_address));
-            in_BRANCH_COMPLETE_OOO_ENGINE_FLAG         [i][j]->write(rand()%2);
+            in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE  [i][j]->write(rand()%2);
           }
 
@@ -520 +520 @@
             TEST(Taddress_t,out_BRANCH_COMPLETE_FRONT_END_ADDRESS          [x][j]->read(),
                              in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS         [i][j]->read());
-            TEST(Tcontrol_t,out_BRANCH_COMPLETE_FRONT_END_FLAG             [x][j]->read(),
-                             in_BRANCH_COMPLETE_OOO_ENGINE_FLAG            [i][j]->read());
+            TEST(Tcontrol_t,out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE      [x][j]->read(),
+                             in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE     [i][j]->read());
             TEST(Tcontrol_t,out_BRANCH_COMPLETE_OOO_ENGINE_ACK             [i][j]->read(),
                              in_BRANCH_COMPLETE_FRONT_END_ACK              [x][j]->read());
@@ -674 +674 @@
   DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_DEPTH           ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
   DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ADDRESS         ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
-  DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_FLAG            ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
+  DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE     ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
   DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]);
   DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_VAL            ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
@@ -682 +682 @@
   DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH          ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
   DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS        ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
-  DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_FLAG           ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
+  DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE    ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
   DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]);
   DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_VAL                ,_param->_nb_front_end);