Ignore:
Timestamp:
Dec 31, 2008, 11:18:08 AM (16 years ago)
Author:
rosiere
Message:

1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...)
2) Change VHDL Execute_queue -> use Generic/Queue?
3) Complete document on VHDL generation
4) Add soc test

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_branch_complete.cpp

    r88 r98  
    5151          PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_DEPTH      [num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH      [i][j]));
    5252          PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ADDRESS    [num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS    [i][j]));
    53           PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_FLAG       [num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_FLAG       [i][j]));
     53          PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE[num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE[i][j]));
    5454          PORT_WRITE(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION [i][j], PORT_READ(in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION [num_front_end][j]));
    5555        }
Note: See TracChangeset for help on using the changeset viewer.