Ignore:
Timestamp:
Dec 31, 2008, 11:18:08 AM (16 years ago)
Author:
rosiere
Message:

1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...)
2) Change VHDL Execute_queue -> use Generic/Queue?
3) Complete document on VHDL generation
4) Add soc test

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp

    r88 r98  
    226226    Tgeneral_data_t imm        = unsigned(param->_size_data,op->_immediat);
    227227
     228    log_printf(TRACE,Functionnal_unit,FUNCTION,"  * data_rc     : %d",op->_data_rc);
     229    log_printf(TRACE,Functionnal_unit,FUNCTION,"  * f_in        : %d",f_in);
     230
    228231    // Result
    229232    op->_timing       = param->_timing[op->_type][op->_operation];
     
    233236    op->_no_sequence  = f_in == 0;
    234237    op->_address      = imm;
     238
     239    log_printf(TRACE,Functionnal_unit,FUNCTION,"  * no_sequence : %d",op->_no_sequence);
    235240  };
    236241
     
    664669
    665670    spr_address_t   spr_addr   = reg->_spr_access_mode->translate_address(addr);
    666    
     671
    667672    // Test if this group is implemented in this functionnal_unit
    668673    if (reg->_spr_access_mode->valid(spr_addr))
Note: See TracChangeset for help on using the changeset viewer.