Changeset 98 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp

Timestamp:

Dec 31, 2008, 11:18:08 AM (16 years ago)

Author:

rosiere

Message:

1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...)
2) Change VHDL Execute_queue -> use Generic/Queue?
3) Complete document on VHDL generation
4) Add soc test

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp (modified) (2 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp

@@ -22 +22 @@
   {
     log_begin(Reexecute_unit,FUNCTION);
+    log_function(Reexecute_unit,FUNCTION,_name.c_str());
 
     if (PORT_READ(in_NRESET) == 0)
@@ -135 +136 @@
       }
 
+#if ((DEBUG >= DEBUG_TRACE) and DEBUG_Reexecute_unit)
+    log_printf(TRACE,Reexecute_unit,FUNCTION,"  * Dump Reexecute_queue");
+
+    for (uint32_t i=0; i<_param->_nb_bank; ++i)
+      {
+        uint32_t j=0;
+        for (std::list<entry_t *>::iterator it=_reexecute_queue[i].begin();
+             it!=_reexecute_queue[i].end();
+             ++it)
+          {
+            log_printf(TRACE,Reexecute_unit,FUNCTION,"  [%.4d][%.4d] %.4d %.4d %.4d, %.1d %.1d, %.4d %.4d, %.8x (%.2d %.4d) %.8x, %.1d %.5d, %s",
+                       i,
+                       j,
+                       (*it)->context_id    ,
+                       (*it)->front_end_id  ,
+                       (*it)->packet_id     ,
+                       (*it)->spr_wen       ,
+                       (*it)->reexecute     ,
+                       (*it)->type          ,
+                       (*it)->operation     ,
+                       (*it)->address       ,
+                      ((*it)->address >> _param->_shift_spr_num_group) & _param->_mask_spr_num_group,
+                      ((*it)->address                                ) & _param->_mask_spr_num_reg  ,
+                       (*it)->data          ,
+                       (*it)->write_rd      ,
+                       (*it)->num_reg_rd    ,
+                       toString((*it)->state).c_str());
+
+            ++j;
+          }
+      }
+//     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+//   private   : std::list<entry_t *>          * _reexecute_queue                         ;//[nb_bank]
+  typedef struct 
+  {
+  } entry_t;
+
+#endif
+
 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
     end_cycle ();