#11 closed enhancement (fixed)
Handle exceptions through a context switch
Reported by: | Nicolas Pouillon | Owned by: | Nicolas Pouillon |
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Priority: | minor | Milestone: | Preemptive scheduler usage |
Component: | hexo | Keywords: | |
Cc: |
Description (last modified by )
There are two main types of exception/interrupts:
- hardware interrupts
- program exception (sysreq, faults, traps, ...)
We'll need to be able to switch from a task to another when handling exceptions, this is because of different needs, but in the end is wanted:
- syscall triggering a device action, thus making the task non-eligible to scheduling until the request ends
- syscall begin sched_switch() or yield()
- page fault triggering a page refill
Sometimes for hardware interrupts, we want to be able to switch tasks as well (eg timer + preempt)
Unfortunately, we cant do most of these jobs directly from the exception handlers because some CPUs (arm) use a special stack pointer when handling interrupts and exceptions. We dont want to loose time in IRQ processing, so we'll spend more time in exception processing.
We could handle all this a portable and easy way if we switched back to kernel mode (not exception or user). On exception/syscall, we can switch to other kernel-mode threads.
Optional exception:
This does not concern IRQs, which must be as-quick as possible. But as we sometimes have to switch threads on IRQ, we should add a mecanism allowing the IRQ handler to request a system service ASAP. Then directly in the asm IRQ handling code, we can detect this service request, and make the IRQ handler jump to the syscall code rather than returning to the user code.
Attachments (7)
Change History (11)
comment:1 Changed 15 years ago by
Description: | modified (diff) |
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comment:2 Changed 14 years ago by
Description: | modified (diff) |
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Changed 14 years ago by
Attachment: | mips_cpu_switching.diff added |
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Mips support patch + hexo factorization
Changed 14 years ago by
Attachment: | exception.2.diff added |
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Same, improved with PPC support, tried & tested through automated builds
Changed 14 years ago by
Attachment: | exception.3.diff added |
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Same, improved with PPC support, tried & tested through automated builds, with correct ARM init
Changed 14 years ago by
Attachment: | exception.5.diff added |
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Close to final version ? with IRQ disabling support
comment:4 Changed 14 years ago by
Milestone: | → Preempt merge |
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Main handling
[1] change la pile user en pile kernel, save l'état du proc [2] change le mode du proc en kernel, IRQ masqués [3] repasse le proc en mode exception [4] repasse le proc en mode user + gestion d'exceptions