[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM NGOUNOU |
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| 4 | -- |
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| 5 | -- Create Date: 05:52:25 06/21/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: CORE_MPI - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | Library NocLib; |
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| 22 | use IEEE.STD_LOGIC_1164.ALL; |
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| 23 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 25 | use NocLib.CoreTypes.all; |
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| 26 | ---- Uncomment the following library declaration if instantiating |
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| 27 | ---- any Xilinx primitives in this code. |
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| 28 | --library UNISIM; |
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| 29 | --use UNISIM.VComponents.all; |
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| 30 | |
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| 31 | entity CORE_MPI is |
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| 32 | Port ( |
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| 33 | clk : in STD_LOGIC; |
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| 34 | reset : in STD_LOGIC; |
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| 35 | clkout : out std_logic; |
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| 36 | instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 37 | instruction_en : in STD_LOGIC; --valide l'instruction |
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| 38 | instruction_fifo_full : out STD_LOGIC; |
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| 39 | ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 40 | barrier_completed : out STD_LOGIC; |
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| 41 | packet_received : out STD_LOGIC; |
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| 42 | packet_ack : in std_logic; |
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| 43 | PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); --le resultat de l'exécution |
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| 44 | ram_we : out STD_LOGIC; |
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| 45 | ram_en : out STD_LOGIC; |
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| 46 | ram_address_rd : out STD_LOGIC_VECTOR (15 downto 0); |
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| 47 | ram_address_wr : out STD_LOGIC_VECTOR (15 downto 0); |
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| 48 | ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 49 | hold_req : out STD_Logic; --requete vers application |
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| 50 | hold_ack : in STD_Logic; --autorisation par l'application |
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| 51 | switch_port_in_cmd_en : out std_logic; |
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| 52 | switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 53 | switch_port_in_wr_en : out STD_LOGIC; |
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| 54 | switch_port_in_full : in STD_LOGIC; |
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| 55 | switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 56 | switch_port_out_rd_en : out STD_LOGIC; |
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| 57 | switch_port_in_empty : in STD_LOGIC; |
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| 58 | switch_port_out_data_vailaible : in STD_LOGIC |
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| 59 | |
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| 60 | |
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| 61 | ); |
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| 62 | |
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| 63 | end CORE_MPI; |
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| 64 | |
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| 65 | architecture Structural of CORE_MPI is |
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| 66 | --déclaration des types |
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| 67 | type Type_Noc is |
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| 68 | record |
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| 69 | port_in_cmd_en : std_logic; |
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| 70 | port_out_data : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 71 | port_in_wr_en : STD_LOGIC; |
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| 72 | port_in_empty : STD_LOGIC; |
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| 73 | port_in_full : STD_LOGIC; |
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| 74 | port_in_data : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 75 | port_out_rd_en : STD_LOGIC; |
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| 76 | port_out_data_available : STD_LOGIC; |
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| 77 | end record; |
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| 78 | -- déclaration des composants MPI |
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| 79 | |
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| 80 | COMPONENT FIFO_64_FWFT |
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| 81 | PORT( |
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| 82 | clk : IN std_logic; |
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| 83 | din : IN std_logic_vector(Word-1 downto 0); |
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| 84 | rd_en : IN std_logic; |
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| 85 | srst : IN std_logic; |
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| 86 | wr_en : IN std_logic; |
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| 87 | dout : OUT std_logic_vector(Word-1 downto 0); |
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| 88 | empty : OUT std_logic; |
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| 89 | full : OUT std_logic |
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| 90 | ); |
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| 91 | END COMPONENT; |
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| 92 | COMPONENT load_instr |
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| 93 | Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 94 | Instruction_en : in STD_LOGIC; |
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| 95 | clk : in STD_LOGIC; |
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| 96 | reset : in STD_LOGIC; |
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| 97 | dma_rd_grant : in STD_LOGIC; |
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| 98 | dma_rd_request : out STD_LOGIC; |
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| 99 | instruction_ack : out STD_LOGIC; |
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| 100 | fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 101 | fifo_wr :out std_logic; |
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| 102 | fifo_full : in STD_LOGIC; |
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| 103 | copying : out std_logic; |
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| 104 | Ram_rd_en : out STD_LOGIC; |
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| 105 | ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 106 | ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0)); |
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| 107 | end component; |
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| 108 | COMPONENT DMA_ARBITER |
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| 109 | PORT( |
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| 110 | |
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| 111 | clk : IN std_logic; |
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| 112 | reset : IN std_logic; |
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| 113 | dma_rd_request : IN std_logic_vector(3 downto 0); |
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| 114 | data_wr_in : IN std_logic_vector(Word-1 downto 0); |
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| 115 | data_rd_out : out std_logic_vector(Word-1 downto 0); |
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| 116 | address_rd : IN std_logic_vector(15 downto 0); |
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| 117 | address_wr : IN std_logic_vector(15 downto 0); |
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| 118 | |
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| 119 | dma_wr_request : IN std_logic_vector(3 downto 0); |
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| 120 | address_out_rd : OUT std_logic_vector(15 downto 0); |
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| 121 | address_out_wr : OUT std_logic_vector(15 downto 0); |
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| 122 | ram_en : OUT std_logic; |
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| 123 | ram_we : OUT std_logic; |
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| 124 | hold_req : out STD_Logic; --requete vers application |
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| 125 | hold_ack : in STD_Logic; --autorisation par l'application |
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| 126 | data_wr_mem : OUT std_logic_vector(Word-1 downto 0); |
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| 127 | data_rd_mem : IN std_logic_vector(Word-1 downto 0); |
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| 128 | dma_wr_grant : OUT std_logic_vector(3 downto 0); |
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| 129 | dma_rd_grant : OUT std_logic_vector(3 downto 0) |
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| 130 | ); |
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| 131 | END COMPONENT; |
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| 132 | |
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| 133 | COMPONENT EX1_FSM |
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| 134 | PORT( |
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| 135 | clk : IN std_logic; |
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| 136 | reset : IN std_logic; |
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| 137 | |
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| 138 | pid : in std_logic_vector (3 downto 0); --port id |
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| 139 | nprocs : in std_logic_vector (3 downto 0); -- la taille du Noc |
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| 140 | instruction_en : in std_logic; |
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| 141 | fifo_empty : IN std_logic; |
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| 142 | fifo_data_out : IN std_logic_vector(Word-1 downto 0); |
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| 143 | fifo_rd_en : OUT std_logic; |
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[39] | 144 | fifo_src : IN STD_LOGIC; |
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[15] | 145 | ram_data_in : IN std_logic_vector(Word-1 downto 0); |
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| 146 | ram_data_out : out std_logic_vector(Word-1 downto 0); |
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| 147 | dma_rd_grant : IN std_logic; |
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| 148 | dma_wr_grant : IN std_logic; |
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| 149 | dma_wr_request : OUT std_logic; |
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| 150 | dma_rd_request : OUT std_logic; |
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| 151 | ram_address : OUT std_logic_vector(15 downto 0); |
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| 152 | ram_rd,ram_wr : out std_logic; |
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| 153 | |
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| 154 | priority_rotation : OUT std_logic; |
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| 155 | |
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| 156 | switch_port_in_data : OUT std_logic_vector(Word-1 downto 0); |
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| 157 | switch_port_in_wr_en : OUT std_logic; |
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| 158 | switch_port_in_full : IN std_logic; |
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| 159 | Result :out std_logic_vector(Word-1 downto 0); |
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| 160 | AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application |
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| 161 | AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation |
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| 162 | Initialized:in std_logic -- état de la Lib |
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| 163 | ); |
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| 164 | END COMPONENT; |
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| 165 | |
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| 166 | COMPONENT EX2_FSM |
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| 167 | PORT( |
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| 168 | clk : IN std_logic; |
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| 169 | reset : IN std_logic; |
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| 170 | |
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| 171 | instruction_en: in std_logic; |
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| 172 | Initialized : in std_logic; |
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| 173 | |
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| 174 | switch_port_out_rd_en : OUT std_logic ; |
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| 175 | switch_data_available : IN std_logic; |
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| 176 | switch_port_out_data : IN std_logic_vector(Word-1 downto 0); |
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| 177 | AppRank : in STD_LOGIC_VECTOR; |
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| 178 | AppSize : in STD_LOGIC_VECTOR; |
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| 179 | dma_wr_grant : IN std_logic; |
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| 180 | dma_wr_request : OUT std_logic; |
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| 181 | dma_rd_grant : IN std_logic; |
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| 182 | dma_rd_request : OUT std_logic; |
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| 183 | ram_address : OUT std_logic_vector(15 downto 0); |
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| 184 | ram_rd,ram_wr : out std_logic; |
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| 185 | Ram_data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 186 | Ram_data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 187 | fifo_full : IN std_logic; |
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| 188 | fifo_data : OUT std_logic_vector(Word-1 downto 0); |
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| 189 | fifo_wr_en : OUT std_logic; |
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| 190 | --fifo_out : out std_logic_vector; |
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| 191 | |
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| 192 | packet_received : OUT std_logic; |
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| 193 | packet_ack : IN std_logic; |
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| 194 | barrier_completed : OUT std_logic; |
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| 195 | Ready : Out std_logic; |
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| 196 | AppInitAck : in std_logic; |
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| 197 | AppInitReq : out std_logic |
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| 198 | ); |
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| 199 | END COMPONENT; |
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| 200 | |
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| 201 | |
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| 202 | COMPONENT EX3_FSM |
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| 203 | PORT( |
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| 204 | instruction : IN std_logic_vector(Word-1 downto 0); |
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| 205 | clk : IN std_logic; |
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| 206 | reset : IN std_logic; |
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| 207 | Ismain :in std_logic; |
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| 208 | ResOut : OUT std_logic_vector(Word-1 downto 0) |
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| 209 | |
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| 210 | ); |
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| 211 | END COMPONENT; |
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| 212 | |
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| 213 | COMPONENT EX4_FSM |
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| 214 | PORT( |
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| 215 | Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); --permet de lire le FIFO |
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| 216 | Instruction_En : in STD_LOGIC; |
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| 217 | clk : in STD_LOGIC; |
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| 218 | reset : in STD_LOGIC; |
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| 219 | ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 220 | Result_En : out STD_LOGIC; |
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| 221 | NocSize : out STD_LOGIC_VECTOR; |
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| 222 | AppRank : out STD_LOGIC_VECTOR; |
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| 223 | AppSize : out STD_LOGIC_VECTOR; |
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| 224 | IsMain : out STD_LOGIC; |
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| 225 | Initialized : out STD_LOGIC; |
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| 226 | dma_wr_req : out std_logic; |
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| 227 | dma_wr_grant : in std_logic; |
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| 228 | AdrRam : out STD_LOGIC_VECTOR (15 downto 0); --accès au stockage |
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| 229 | WeRam : out STD_LOGIC; --activation de l'écriture en RAM |
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| 230 | DataRam : out STD_LOGIC_VECTOR (Word-1 downto 0);--données des ports |
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| 231 | AppAck : in STD_LOGIC; |
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| 232 | AppReq : in STD_LOGIC; |
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| 233 | PortId : out STD_LOGIC_VECTOR(3 downto 0); |
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| 234 | port_in_cmd_en : out STD_LOGIC; |
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| 235 | port_in_wr_en : out STD_LOGIC; |
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| 236 | port_in_empty : in STD_LOGIC; |
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| 237 | port_in_full : in STD_LOGIC; |
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| 238 | port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 239 | port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 240 | port_out_rd_en : out STD_LOGIC; |
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| 241 | port_out_data_available : in STD_LOGIC); |
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| 242 | END COMPONENT; |
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| 243 | |
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| 244 | COMPONENT EX0_FSM |
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| 245 | PORT( |
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| 246 | clk : in STD_LOGIC; |
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| 247 | reset : in STD_LOGIC; |
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| 248 | |
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| 249 | Initialized : in STD_LOGIC; |
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| 250 | Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 251 | instruction_en: in STD_LOGIC; |
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| 252 | |
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| 253 | ClkRate : in STD_LOGIC_VECTOR ; |
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| 254 | uTimeResult : out STD_LOGIC_VECTOR; |
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| 255 | TickResult : out STD_LOGIC_VECTOR |
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| 256 | ); |
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| 257 | END COMPONENT; |
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| 258 | |
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| 259 | |
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| 260 | COMPONENT MPI_CORE_SCHEDULER |
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| 261 | PORT( |
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| 262 | clk : IN std_logic; |
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| 263 | reset : IN std_logic; |
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| 264 | priority_rotation : IN std_logic; |
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| 265 | instruction_fifo_empty : IN std_logic; |
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| 266 | instruction_fifo_rd_en : OUT std_logic; |
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| 267 | instruction_fifo_data : IN std_logic_vector(Word-1 downto 0); |
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| 268 | instruction_available : OUT std_logic; |
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| 269 | |
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| 270 | get_request_fifo_empty : IN std_logic; |
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| 271 | get_request_fifo_rd_en : OUT std_logic; |
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| 272 | get_request_fifo_data : IN std_logic_vector(Word-1 downto 0); |
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| 273 | |
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| 274 | fifo_rd_en : IN std_logic; |
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| 275 | fifo_empty : OUT std_logic; |
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| 276 | fifo_selected : OUT std_logic; |
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| 277 | |
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| 278 | data_out : OUT std_logic_vector(Word-1 downto 0) |
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| 279 | |
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| 280 | |
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| 281 | ); |
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| 282 | END COMPONENT; |
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| 283 | |
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| 284 | -- declaration des signaux d'interconnexion entre les modules du coresignal fifo_sel: std_logic; -- indique l'un des deux fifos d'instructions qui sont prêts |
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| 285 | signal fifo_instr : std_logic; -- une instruction est prête dans les fifos d'instruction |
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| 286 | |
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| 287 | |
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| 288 | signal scheduler_fifo_empty : std_logic; |
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| 289 | signal scheduler_data_out : std_logic_vector(Word-1 downto 0); |
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| 290 | signal dma_arbiter_data_rd_out : std_logic_vector(Word-1 downto 0); |
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| 291 | |
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| 292 | signal scheduler_priority_rotation : std_logic; |
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| 293 | signal scheduler_rd_en : std_logic; |
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| 294 | |
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| 295 | signal dma_data_rd,dma_data_wr : std_logic_vector(Word-1 downto 0); -- bus à 3 états |
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| 296 | signal dma_rd_address,dma_rd_address1,dma_rd_address2 : std_logic_vector(15 downto 0); -- ces bus doivent être gérés en logique 3 états! |
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| 297 | signal dma_rd_address3 : std_logic_vector(15 downto 0); |
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| 298 | signal dma_wr_address1,dma_wr_address3 : std_logic_vector(15 downto 0); |
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| 299 | signal dma_wr_address2,dma_wr_address4 : std_logic_vector(15 downto 0); |
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| 300 | signal dma_wr_address : std_logic_vector(15 downto 0); |
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| 301 | signal switch_port_in_data_signal : std_logic_vector(Word-1 downto 0); |
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| 302 | signal ram_data_out_signal : std_logic_vector(Word-1 downto 0); |
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| 303 | signal weram,rdram,ram_wev,ram_env :std_logic:='0'; |
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| 304 | |
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| 305 | signal instruction_fifo2_signal : std_logic_vector(Word-1 downto 0); |
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| 306 | signal Ex_EN : std_logic_vector(4 downto 1):=(others=>'0'); --active les sous MAE permettant de décoder les instructions MPI |
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| 307 | signal Ex1_RDY,Ex2_RDY,EX3_RDY,EX4_RDY : std_logic; -- indique la fin de l'exécution de la MAE |
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| 308 | signal ex1_ram_rd,ex2_ram_rd,ex4_ram_rd ,Exi_ram_rd: std_logic ; -- validation lecture des données en RAM |
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| 309 | signal ex1_ram_wr,ex2_ram_wr,ex4_ram_wr,Exi_ram_wr : std_logic ; -- validation écriture des données en RAM |
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| 310 | signal Exi_busy : std_logic; |
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| 311 | signal Ex1_Result,Ex4_result : std_logic_vector(Word-1 downto 0); |
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| 312 | |
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| 313 | --================interface DMA avec les modules ====================================== |
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| 314 | signal dma_data_in,Dma_data_in1,dma_data_in2,dma_data_in4 : std_logic_vector(Word-1 downto 0); |
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| 315 | signal dma_data_out : std_logic_vector(Word-1 downto 0); |
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| 316 | signal dma_rd_request :std_logic_vector(4 downto 1):=(others=>'0'); |
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| 317 | signal dma_wr_request :std_logic_vector(4 downto 1):=(others=>'0'); |
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| 318 | signal dma_wr_grant,dma_rd_grant:std_logic_vector(4 downto 1); |
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| 319 | -- |
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| 320 | --====================================================================================== |
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| 321 | --connexion au switch |
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| 322 | |
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| 323 | signal Noc1,NOC2,NOC3 : Type_Noc; -- regroupement des signaux qui vont au Noc |
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| 324 | |
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| 325 | --================================================================ |
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| 326 | --déclaration des signaux d'état du Core |
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| 327 | signal IsMain,SizeSet,RankSet,Initialized,AppReq,AppAck:std_logic; |
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| 328 | signal InitReq,InitReq1,InitReq2 :std_logic; -- demande d'initialisation |
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| 329 | signal InitAck,IAck,Ilatch : std_logic; |
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| 330 | signal MPISize,MyRank : std_logic_vector(3 downto 0); |
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| 331 | signal LibState: std_logic_vector(Word-1 downto 0); --ready,receiving,sending,spawning,rwaiting,swaiting,... |
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| 332 | signal NocSize :std_logic_vector(3 downto 0); |
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| 333 | Signal PortId : std_logic_vector(3 downto 0); |
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| 334 | Signal uClkRate : std_logic_vector(Word-1 downto 0):="00011010"; --50 Mhz |
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| 335 | signal uTimeCount :std_logic_vector(31 downto 0); |
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| 336 | signal TickCount : std_logic_vector(31 downto 0); |
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| 337 | signal RankSize: std_logic_vector(Word-1 downto 0); |
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| 338 | --======================================================== |
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| 339 | --déclaration des signaux permettant d'activer le module |
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| 340 | signal AdrSelect : std_logic_vector(ADRLEN-1 downto 0); |
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| 341 | --======================================================== |
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| 342 | --signal PushOut_d,RankSize,TickUsOut:std_logic_vector; --résultat de l'execution des commandes mpi |
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| 343 | --======================================================== |
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| 344 | --connexion avec les FIFO instructions |
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| 345 | signal fifo1_wr : std_logic; |
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| 346 | signal fifo1_din : std_logic_vector (Word-1 downto 0); |
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| 347 | signal fifo_sel : std_logic; --permet d'arbitrer la priorité de lecture entre les deux fifos |
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| 348 | signal instruction_fifo1_rd_en : std_logic; |
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| 349 | signal fifo1_full : std_logic; |
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| 350 | signal instruction_fifo1_empty : std_logic; |
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| 351 | signal instruction_fifo1_data_out : std_logic_vector(Word-1 downto 0); |
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| 352 | signal instruction_fifo2_rd_en : std_logic; |
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| 353 | signal instruction_fifo2_data_out : std_logic_vector(Word-1 downto 0); |
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| 354 | signal instruction_fifo2_data_in : std_logic_vector(Word-1 downto 0); |
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| 355 | signal instruction_fifo2_wr_en : std_logic; |
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| 356 | signal instruction_fifo2_empty : std_logic; |
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| 357 | signal instruction_fifo2_full : std_logic; |
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| 358 | |
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| 359 | --=========================================================== |
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| 360 | |
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| 361 | begin |
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| 362 | --switch_port_in_data_signal <= ; |
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| 363 | --switch_port_out_data_signal <= ; |
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| 364 | -- istanciation des composants du core MPI |
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| 365 | Instruction_Fifo1: FIFO_64_FWFT PORT MAP( |
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| 366 | clk =>clk, |
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| 367 | din =>fifo1_din, |
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| 368 | rd_en => instruction_fifo1_rd_en, |
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| 369 | srst => reset, |
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| 370 | wr_en => fifo1_wr, |
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| 371 | dout =>instruction_fifo1_data_out, |
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| 372 | empty => instruction_fifo1_empty, |
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| 373 | full => fifo1_full |
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| 374 | ); |
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| 375 | |
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| 376 | Instruction_Fifo2: FIFO_64_FWFT PORT MAP( |
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| 377 | clk =>clk, |
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| 378 | din => instruction_fifo2_data_in , |
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| 379 | rd_en =>instruction_fifo2_rd_en, |
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| 380 | srst =>reset, |
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| 381 | wr_en =>instruction_fifo2_wr_en, |
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| 382 | dout =>instruction_fifo2_data_out, |
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| 383 | empty =>instruction_fifo2_empty, |
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| 384 | full => instruction_fifo2_full |
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| 385 | ); |
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| 386 | LD_instr:load_instr PORT MAP ( |
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| 387 | |
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| 388 | Instruction =>Instruction, |
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| 389 | Instruction_en =>Instruction_en, |
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| 390 | clk =>clk, |
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| 391 | reset =>reset, |
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| 392 | dma_rd_grant =>dma_rd_grant(3), |
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| 393 | dma_rd_request =>dma_rd_request(3), |
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| 394 | copying=> Exi_busy, |
---|
| 395 | instruction_ack =>iack, --indique la fin de la copie d'une instruction dans le FIFO |
---|
| 396 | fifo_din => fifo1_din, |
---|
| 397 | fifo_wr => fifo1_wr, |
---|
| 398 | fifo_full =>fifo1_full, |
---|
| 399 | Ram_rd_en=> Exi_ram_rd, |
---|
| 400 | ram_address_rd => dma_rd_address3, |
---|
| 401 | ram_data =>dma_data_out --sortie DMA |
---|
| 402 | ); |
---|
| 403 | |
---|
| 404 | pushout(0)<=ILatch; |
---|
| 405 | pushout(1)<=IsMain; |
---|
| 406 | pushout(2)<=SizeSet; |
---|
| 407 | pushout(3)<=RankSet; |
---|
| 408 | pushout(4)<=Initialized; |
---|
| 409 | pushout(5)<=Ex1_result(1); -- |
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| 410 | |
---|
| 411 | |
---|
| 412 | MPI_CORE_EX0_FSM: EX0_FSM PORT MAP( |
---|
| 413 | instruction => instruction_fifo1_data_out, |
---|
| 414 | instruction_en=> '1', |
---|
| 415 | uTimeResult => uTimeCount, |
---|
| 416 | TickResult => TickCount, |
---|
| 417 | Initialized => Initialized, -- indique si la l'appel à init a été concluant |
---|
| 418 | ClkRate => uClkRate, |
---|
| 419 | clk =>clk , |
---|
| 420 | reset => reset |
---|
| 421 | ); |
---|
| 422 | MPI_CORE_EX1_FSM: EX1_FSM PORT MAP( |
---|
| 423 | clk =>clk , |
---|
| 424 | reset =>reset, |
---|
| 425 | pid => MyRank, --port Id |
---|
| 426 | nprocs=>MPISize, -- à revoir dans certains cas ou tous les PEs ne sont pas connectés |
---|
| 427 | fifo_empty => scheduler_fifo_empty , |
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| 428 | fifo_data_out =>scheduler_data_out, |
---|
| 429 | fifo_rd_en =>scheduler_rd_en, |
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[39] | 430 | fifo_src =>fifo_sel, |
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[15] | 431 | priority_rotation => scheduler_priority_rotation, |
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| 432 | |
---|
| 433 | instruction_en=>Ex_en(1), --active le module |
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| 434 | |
---|
| 435 | switch_port_in_full =>Noc1.port_in_full, --ces signaux doivent être contrôlés en 3 state logic |
---|
| 436 | switch_port_in_data =>Noc1.port_in_data, |
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| 437 | switch_port_in_wr_en =>Noc1.Port_in_wr_en , |
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| 438 | |
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| 439 | Ram_rd => ex1_ram_rd, |
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| 440 | Ram_wr =>ex1_ram_wr, |
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| 441 | ram_data_in =>dma_data_out, |
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| 442 | Ram_data_out =>dma_data_in1, |
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| 443 | ram_address=>dma_wr_address1, |
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| 444 | --ram_address =>dma_rd_address2, --la même adresse sert pour la lecture ou l'écriture |
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| 445 | dma_rd_request =>dma_rd_request(1), |
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| 446 | dma_wr_request =>dma_wr_request(1), |
---|
| 447 | dma_rd_grant =>dma_rd_grant(1) , |
---|
| 448 | dma_wr_grant =>dma_wr_grant(1) , |
---|
| 449 | |
---|
| 450 | AppInitReq => InitReq1, -- requête d'initialisation de l'application |
---|
| 451 | AppInitAck =>Ex4_rdy , -- Acquitement d'initialisation |
---|
| 452 | Initialized=>Initialized, -- état de la Lib |
---|
| 453 | Result => Ex1_Result -- le résultat de l'exécution |
---|
| 454 | ); |
---|
| 455 | instruction_fifo_full<=fifo1_full; |
---|
| 456 | dma_rd_address1<=dma_wr_address1; --la même adresse sert pour la lecture ou l'écriture en RAM |
---|
| 457 | |
---|
| 458 | -- détermination de l'activation des module |
---|
| 459 | --scheduler_priority_rotation<=not(Ex1_rdy); |
---|
| 460 | Instr_Rdy:process(Iack,fifo_instr,fifo_sel)--A qoui sert encore ce processus (26/10/12) ???? |
---|
| 461 | begin |
---|
| 462 | case fifo_sel is |
---|
| 463 | when '0' => |
---|
| 464 | |
---|
| 465 | if rising_edge(Iack) then |
---|
| 466 | Ex_en(1)<= fifo_instr; |
---|
| 467 | |
---|
| 468 | end if; |
---|
| 469 | --Ex_en(2)<='0'; |
---|
| 470 | |
---|
| 471 | when '1' => |
---|
| 472 | Ex_en(1)<=fifo_instr; |
---|
| 473 | --Ex_en(2)<= fifo_instr; |
---|
| 474 | when others => |
---|
| 475 | Ex_en(1)<='0'; |
---|
| 476 | --Ex_en(2)<= '0'; |
---|
| 477 | |
---|
| 478 | end case; |
---|
| 479 | end process; |
---|
| 480 | |
---|
| 481 | Active_proc:Process(Ex1_Result) --active la réception lorsqu' Put ou un Get ou un Init a été effectué |
---|
| 482 | begin |
---|
| 483 | if Ex1_result(0)='1' or Ex1_result(1)='1' or Ex1_result(2)='1' then |
---|
| 484 | Ex_en(2)<='1'; |
---|
| 485 | else |
---|
| 486 | --Ex_en(2)<='0'; |
---|
| 487 | end if; |
---|
| 488 | |
---|
| 489 | end process; |
---|
| 490 | |
---|
| 491 | Latch_instr:process (clk,Iack,Exi_busy) |
---|
| 492 | begin |
---|
| 493 | if rising_edge(clk) then |
---|
| 494 | |
---|
| 495 | Ilatch<=IAck; |
---|
| 496 | |
---|
| 497 | end if; |
---|
| 498 | |
---|
| 499 | end process; |
---|
| 500 | --Ex_en(2)<=Initialized; --- Me pose des soucis en ce moment ??? |
---|
| 501 | Ex_en(3)<='0'; |
---|
| 502 | Ex_en(4)<= '1' when InitReq='1' else '0'; |
---|
| 503 | Appreq<=Ex_en(4); --signal d'activation de la MAE Init |
---|
| 504 | InitReq<=(not(Initialized) and InitReq1) or InitReq2; -- deux cas permettent d'activer l'initialisation |
---|
| 505 | AppAck<=Ex1_result(0); -- signal init completed |
---|
| 506 | -- soit une requête du PE soit une requête du Core |
---|
| 507 | |
---|
| 508 | |
---|
| 509 | MPI_CORE_EX2_FSM: EX2_FSM PORT MAP( |
---|
| 510 | |
---|
| 511 | clk =>clk, |
---|
| 512 | reset =>reset, |
---|
| 513 | instruction_en=>Ex_en(2), |
---|
| 514 | Ready =>Ex2_rdy, --signale que le module est disponible |
---|
| 515 | fifo_full =>instruction_fifo2_full, |
---|
| 516 | |
---|
| 517 | fifo_wr_en => instruction_fifo2_wr_en, |
---|
| 518 | fifo_data => instruction_fifo2_data_in, |
---|
| 519 | |
---|
| 520 | switch_port_out_rd_en => Noc2.port_out_rd_en, |
---|
| 521 | switch_data_available =>Noc2.port_out_data_available, |
---|
| 522 | switch_port_out_data =>Noc2.port_out_data , |
---|
| 523 | -- il manque un signal pour valider l'accès à la RAM |
---|
| 524 | dma_wr_request =>dma_wr_request(2), |
---|
| 525 | dma_wr_grant =>dma_wr_grant(2), |
---|
| 526 | dma_rd_request =>dma_rd_request(2), |
---|
| 527 | dma_rd_grant =>dma_rd_grant(2), |
---|
| 528 | ram_address =>dma_wr_address2, |
---|
| 529 | Ram_rd => ex2_ram_rd, |
---|
| 530 | Ram_wr =>ex2_ram_wr, |
---|
| 531 | Ram_data_out=> Dma_data_in2, |
---|
| 532 | Ram_data_in => Dma_data_out, |
---|
| 533 | packet_received =>packet_received, |
---|
| 534 | packet_ack => packet_ack, |
---|
| 535 | barrier_completed =>barrier_completed, |
---|
| 536 | AppRank =>MyRank, |
---|
| 537 | AppSize =>MPISize, |
---|
| 538 | AppInitReq => InitReq2, -- requête d'initialisation de l'application |
---|
| 539 | AppInitAck =>Ex4_rdy , -- Acquitement d'initialisation |
---|
| 540 | Initialized=>Initialized |
---|
| 541 | |
---|
| 542 | ); |
---|
| 543 | Dma_rd_address2<=Dma_wr_address2; |
---|
| 544 | ICI_MPI_CORE_EX3_FSM: EX3_FSM PORT MAP( |
---|
| 545 | instruction => instruction, |
---|
| 546 | ResOut => RankSize, |
---|
| 547 | clk =>clk , |
---|
| 548 | IsMain=>IsMain, |
---|
| 549 | reset => reset |
---|
| 550 | ); |
---|
| 551 | MPI_CORE_EX4_FSM :EX4_FSM PORT MAP ( |
---|
| 552 | Instruction => Instruction, --STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
| 553 | Instruction_En =>Ex_en(4), -- ='1' lorsque ce module est sollicité |
---|
| 554 | clk =>clk, |
---|
| 555 | reset =>reset, |
---|
| 556 | ResultOut =>Ex4_Result, --STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
| 557 | Result_En =>Ex4_Rdy, -- ='1' lorsque fin de l'exécution du module |
---|
| 558 | NocSize =>NocSize, |
---|
| 559 | AppRank =>MyRank, |
---|
| 560 | AppSize =>MPISize, |
---|
| 561 | IsMain =>IsMain, |
---|
| 562 | Initialized =>Initialized, |
---|
| 563 | AdrRam =>dma_wr_Address4, --accès au stockage |
---|
| 564 | WeRam =>Ex4_Ram_wr, --activation de l'écriture en RAM |
---|
| 565 | DataRam =>Dma_data_in4, --données à écrire en RAM |
---|
| 566 | DMA_wr_Req => dma_wr_request(4), |
---|
| 567 | DMA_wr_grant => dma_wr_grant(4), |
---|
| 568 | AppAck =>AppAck, |
---|
| 569 | AppReq =>AppReq, |
---|
| 570 | PortId=>PortId, |
---|
| 571 | port_in_cmd_en => Noc3.port_in_cmd_en, |
---|
| 572 | port_in_wr_en =>Noc3.port_in_wr_en, |
---|
| 573 | port_in_empty =>Noc3.port_in_empty, |
---|
| 574 | port_in_full =>Noc3.port_in_full, |
---|
| 575 | port_in_data =>Noc3.port_in_data, |
---|
| 576 | port_out_data =>Noc3.port_out_data, |
---|
| 577 | port_out_rd_en =>Noc3.port_out_rd_en, |
---|
| 578 | port_out_data_available =>Noc3.port_out_data_available |
---|
| 579 | |
---|
| 580 | |
---|
| 581 | ); |
---|
| 582 | --=============Mux des signaux d'accès à la RAM========= |
---|
| 583 | ram_we<='1' when (weram='1' and ram_wev ='1') else '0'; -- le contrôleur DMA contrôle directement |
---|
| 584 | Ram_en<= '1' when (rdram ='1' or weram='1') else '0'; -- les signaux qui vont vers la RAM |
---|
| 585 | |
---|
| 586 | --dma_data_in <=dma_data_in1 or dma_data_in2; |
---|
| 587 | --dma_data_out <=dma_data_out1 or dma_data_out2; |
---|
| 588 | mux_ad_ram_rd:process (dma_rd_grant,dma_rd_address1,dma_rd_address2,dma_rd_address3, |
---|
| 589 | ex1_ram_rd, Ex2_ram_rd, Exi_ram_rd ) |
---|
| 590 | begin |
---|
| 591 | case dma_rd_grant is |
---|
| 592 | when "0001" => dma_rd_address <= dma_rd_address1; |
---|
| 593 | rdram<= ex1_ram_rd; |
---|
| 594 | when "0010" => dma_rd_address <= dma_rd_address2; |
---|
| 595 | rdram<= ex2_ram_rd; |
---|
| 596 | when "0100" => dma_rd_address <= dma_rd_address3; |
---|
| 597 | rdram<= exi_ram_rd; |
---|
| 598 | -- when "1000" => dma_rd_address <= <input4>; |
---|
| 599 | when others => dma_rd_address <= (others =>'Z'); |
---|
| 600 | rdram<='0'; |
---|
| 601 | end case; |
---|
| 602 | end process; |
---|
| 603 | mux_ad_ram_wr:process (dma_wr_grant,dma_wr_address1,dma_wr_address2,dma_wr_address4,Dma_data_in1,Dma_data_in2,Dma_data_in4,ex2_ram_wr,ex4_ram_wr) |
---|
| 604 | begin |
---|
| 605 | case dma_wr_grant is |
---|
| 606 | |
---|
| 607 | when "0001" => dma_wr_address <= dma_wr_address1; |
---|
| 608 | weram<=ex1_ram_wr ; |
---|
| 609 | Dma_data_in<=Dma_data_in1; |
---|
| 610 | when "0010" => dma_wr_address <= dma_wr_address2; |
---|
| 611 | weram<=ex2_ram_wr ; |
---|
| 612 | Dma_data_in<=Dma_data_in2; |
---|
| 613 | when "1000" => dma_wr_address <= dma_wr_address4; |
---|
| 614 | weram<=ex4_ram_wr; |
---|
| 615 | Dma_data_in<=Dma_data_in4; |
---|
| 616 | -- when "0100" => dma_rd_address <= <input3>; |
---|
| 617 | -- when "1000" => dma_rd_address <= <input4>; |
---|
| 618 | when others => dma_wr_address <= (others =>'Z'); |
---|
| 619 | weram<='0'; |
---|
| 620 | end case; |
---|
| 621 | end process; |
---|
| 622 | --====================================================== |
---|
| 623 | |
---|
| 624 | --=================Mux des signaux qui vont au switch============ |
---|
| 625 | clkout<=clk; -- permettra le lien avec le module du switch |
---|
| 626 | |
---|
| 627 | NOC1.port_out_data<=switch_port_out_data; |
---|
| 628 | NOC1.port_out_data_available<=switch_port_out_data_vailaible; |
---|
| 629 | NOC1.port_in_empty<=switch_port_in_empty; |
---|
| 630 | NOC1.port_in_full<=switch_port_in_full; |
---|
| 631 | |
---|
| 632 | NOC2.port_out_data<=switch_port_out_data; |
---|
| 633 | NOC2.port_out_data_available<=switch_port_out_data_vailaible; |
---|
| 634 | NOC2.port_in_empty<=switch_port_in_empty; |
---|
| 635 | NOC2.port_in_full<=switch_port_in_full; |
---|
| 636 | |
---|
| 637 | NOC3.port_out_data<=switch_port_out_data; |
---|
| 638 | NOC3.port_out_data_available<=switch_port_out_data_vailaible; |
---|
| 639 | NOC3.port_in_empty<=switch_port_in_empty; |
---|
| 640 | NOC3.port_in_full<=switch_port_in_full; |
---|
| 641 | mux_Noc:process (Ex_en,Noc1,Noc2,Noc3) |
---|
| 642 | |
---|
| 643 | begin |
---|
| 644 | |
---|
| 645 | case Ex_en is |
---|
| 646 | |
---|
| 647 | when"0001" => |
---|
| 648 | switch_port_in_data <=Noc1.port_in_data; |
---|
| 649 | switch_port_out_rd_en<=NOC2.port_out_rd_en; |
---|
| 650 | switch_port_in_wr_en <=NOC1.port_in_wr_en; |
---|
| 651 | switch_port_in_cmd_en <='0'; |
---|
| 652 | when "0010" => |
---|
| 653 | switch_port_in_data <=Noc1.port_in_data; |
---|
| 654 | switch_port_out_rd_en<=NOC2.port_out_rd_en; |
---|
| 655 | switch_port_in_wr_en <=NOC1.port_in_wr_en; |
---|
| 656 | switch_port_in_cmd_en <='0'; |
---|
| 657 | when"0011" => |
---|
| 658 | switch_port_in_data <=Noc1.port_in_data; |
---|
| 659 | switch_port_out_rd_en<=NOC2.port_out_rd_en; |
---|
| 660 | switch_port_in_wr_en <=NOC1.port_in_wr_en; |
---|
| 661 | switch_port_in_cmd_en <='0'; |
---|
| 662 | when "1001" | "1010" => --ca où un appel à init est effectué |
---|
| 663 | switch_port_in_data <=Noc3.port_in_data; |
---|
| 664 | switch_port_out_rd_en<=NOC3.port_out_rd_en; |
---|
| 665 | switch_port_in_wr_en <=NOC3.port_in_wr_en; |
---|
| 666 | switch_port_in_cmd_en <=NOC3.port_in_cmd_en; |
---|
| 667 | |
---|
| 668 | when others => |
---|
| 669 | switch_port_in_data <=(others=>'0'); |
---|
| 670 | switch_port_out_rd_en<='0'; |
---|
| 671 | switch_port_in_wr_en <='0'; |
---|
| 672 | switch_port_in_cmd_en <='0'; |
---|
| 673 | end case; |
---|
| 674 | end process; |
---|
| 675 | |
---|
| 676 | |
---|
| 677 | --=============================================================== |
---|
| 678 | MPI_CORE_DMA_ARBITER: DMA_ARBITER PORT MAP( |
---|
| 679 | clk =>clk, |
---|
| 680 | reset =>reset, |
---|
| 681 | |
---|
| 682 | data_wr_mem => ram_data_in, --vers RAM |
---|
| 683 | |
---|
| 684 | data_rd_mem => Ram_data_out, --- Vers RAM |
---|
| 685 | address_rd =>dma_rd_address, |
---|
| 686 | address_wr =>dma_wr_address, |
---|
| 687 | address_out_rd =>ram_address_rd, |
---|
| 688 | address_out_wr =>ram_address_wr, |
---|
| 689 | ram_en => ram_env, --validation lecture |
---|
| 690 | ram_we =>ram_wev, --validation écriture |
---|
| 691 | hold_req=>hold_req,--demande de bus à l'application |
---|
| 692 | hold_ack=>hold_ack, -- libération du bus RAM par l'application |
---|
| 693 | |
---|
| 694 | data_rd_out => Dma_data_out, --vers périphérique |
---|
| 695 | data_wr_in =>Dma_data_in, --vers périphérique |
---|
| 696 | dma_wr_grant =>dma_wr_grant, |
---|
| 697 | dma_rd_request => dma_rd_request, |
---|
| 698 | dma_rd_grant => dma_rd_grant, |
---|
| 699 | dma_wr_request => dma_wr_request |
---|
| 700 | ); |
---|
| 701 | |
---|
| 702 | |
---|
| 703 | CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP( -- permet de sélectionner la source de l'instruction |
---|
| 704 | -- qui sera exécutée par la MAE EX1 |
---|
| 705 | clk => clk, |
---|
| 706 | reset => reset, |
---|
| 707 | priority_rotation =>scheduler_priority_rotation, |
---|
| 708 | instruction_fifo_empty =>instruction_fifo1_empty, |
---|
| 709 | get_request_fifo_empty => instruction_fifo2_empty, |
---|
| 710 | instruction_fifo_rd_en =>instruction_fifo1_rd_en, |
---|
| 711 | get_request_fifo_rd_en =>instruction_fifo2_rd_en , |
---|
| 712 | instruction_fifo_data =>instruction_fifo1_data_out, |
---|
| 713 | get_request_fifo_data =>instruction_fifo2_data_out, |
---|
| 714 | fifo_selected =>fifo_sel, |
---|
| 715 | instruction_available => fifo_instr, |
---|
| 716 | fifo_empty => scheduler_fifo_empty, |
---|
| 717 | fifo_rd_en =>scheduler_rd_en, |
---|
| 718 | data_out => scheduler_data_out |
---|
| 719 | ); |
---|
| 720 | |
---|
| 721 | end structural; |
---|
| 722 | |
---|