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EX2_FSM.vhd @ 39

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1	----------------------------------------------------------------------------------
2	-- Company: GRIIA - ETIS
3	-- Engineer: GAMOM, KIEGAING
4	--
5	-- Create Date: 01:02:10 06/17/2011
6	-- Design Name:
7	-- Module Name: EX2_FSM - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	-- machine a etat qui execute la reception des packet dans le core mpi
13	-- Dependencies:
14	--ss
15	-- Revision: 26/01/2012
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	library NocLib ;
22	use IEEE.STD_LOGIC_1164.ALL;
23	use IEEE.Numeric_std.ALL;
24	use IEEE.STD_LOGIC_UNSIGNED.ALL;
25	use Work.Packet_type.ALL;
26	use NocLib.CoreTypes.all;
27	---- Uncomment the following library declaration if instantiating
28	---- any Xilinx primitives in this code.
29	--library UNISIM;
30	--use UNISIM.VComponents.all;
31
32	entity EX2_FSM is
33
34	generic (
35	pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur
36	nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1
37	);
38	Port ( clk : in STD_LOGIC;
39	reset : in STD_LOGIC;
40
41	Instruction_en : in std_logic;
42
43	dma_wr_grant : in STD_LOGIC;
44	dma_wr_request : out STD_LOGIC;
45	dma_rd_grant : in STD_LOGIC;
46	dma_rd_request : out STD_LOGIC;
47	ram_rd : out std_logic;
48	ram_wr : out std_logic;
49	ram_address : out std_logic_vector(ADRLEN-1 downto 0);
50	Ram_data_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
51	Ram_data_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
52
53	fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0);
54	fifo_wr_en : out STD_LOGIC;
55	fifo_full : in STD_LOGIC;
56
57	AppRank : in STD_LOGIC_VECTOR(3 downto 0);
58	AppSize : in STD_LOGIC_VECTOR(3 downto 0);
59	packet_received : out STD_LOGIC;
60	packet_ack : in STD_LOGIC;
61	barrier_completed : out STD_LOGIC;
62	Ready : Out std_logic;
63	AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application
64	AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation
65	Initialized:in std_logic ; -- état de la Lib
66
67	switch_data_available : in STD_LOGIC;
68	switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0);
69	switch_port_out_rd_en : out STD_LOGIC
70
71
72
73	);
74	end EX2_FSM;
75
76	architecture Behavioral of EX2_FSM is
77	-- définition du type etat de la machine à etat
78	type fsm_states is (fetch_packet_type, decode_packet_type, decode_packet_type2,
79	fetch_addresses,execute_spawn,execute_put1,execute_put2,execute_put3 ,execute_put4,
80	execute_put5,execute_get1, execute_get2,execute_get3,execute_get4,
81	execute_barrier1, execute_barrier2, execute_barrier3, execute_barrier4,
82	execute_barrier5, execute_barrier6, execute_barrier7,execute_init1,execute_init2);
83	signal ex2_state_mach :fsm_states;
84	-- machine a etat du module
85	signal packet_type : std_logic_vector(3 downto 0);
86	signal packet_length : std_logic_vector(Word-1 downto 0);
87	signal barrier_counter : std_logic_vector(3 downto 0);
88	signal pading_data,data_to_ram : std_logic_vector(Word-1 downto 0):=(others=>'0');
89	signal n : std_logic_vector(3 downto 0);
90	signal dest_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'Z');
91	signal data_to_write_fifo : std_logic_vector(Word-1 downto 0);
92	signal Ex2_on : std_logic:='0';
93	signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
94
95	begin
96	ram_address <= dest_address;
97	fifo_data <= data_to_write_fifo;
98
99	-- processus de transistion entre les etats
100	fsm_nst_logic : process(clk)
101	variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée
102	variable tempval : std_logic_vector(Word-1 downto 0);
103	begin
104	if rising_edge(clk) then
105	if reset = '1' then
106	ex2_state_mach <= fetch_packet_type;
107	Ex2_on<='0';
108	barrier_counter <= "0000";
109	else
110	Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non
111	case ex2_state_mach is
112	when fetch_packet_type => if switch_data_available ='1' and Ex2_on='1' then --and initialized ='1'
113	ex2_state_mach <= decode_packet_type;
114	packet_type<=switch_port_out_data(7 downto 4);
115	else
116	ex2_state_mach <= fetch_packet_type;
117	end if;
118	when decode_packet_type => if switch_data_available ='0' then
119	ex2_state_mach <= decode_packet_type;
120	else
121	if packet_type = MPI_PUT then
122	packet_length <= switch_port_out_data - 2;
123	n <="0000";
124	ex2_state_mach <= decode_packet_type2;
125	elsif packet_type = MPI_GET then
126	packet_length <=switch_port_out_data-2;
127	ex2_state_mach <= decode_packet_type2;
128	elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
129	packet_length <= switch_port_out_data;
130	n <= "0000";
131	ex2_state_mach <= execute_barrier1;
132	elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then
133	ex2_state_mach <= execute_init1;
134	else
135	ex2_state_mach <= decode_packet_type;
136	end if;
137	end if;
138	when decode_packet_type2 => if packet_type = MPI_PUT then
139	ex2_state_mach <= fetch_addresses;
140	else
141	ex2_state_mach <= execute_get1;
142	end if;
143	when fetch_addresses => if switch_data_available = '1' and n = 0 then
144	dest_address(15 downto 8) <= switch_port_out_data;
145	n <= n + 1;
146	ex2_state_mach <= fetch_addresses;
147	elsif switch_data_available = '1' and n = 1 then
148	dest_address(Word-1 downto 0) <= switch_port_out_data;
149	packet_length <= packet_length - 2;
150	ex2_state_mach <= execute_put1;
151	else
152	ex2_state_mach <= fetch_addresses;
153	end if;
154	-- execution du mpi Init
155	when execute_init1 =>if Initialized='1' then
156	ex2_state_mach<=execute_init2;
157	end if;
158	when execute_init2=> if AppInitAck='1' then
159	ex2_state_mach<=fetch_packet_type;
160	end if;
161	when execute_put1 => if dma_wr_grant = '1' then
162	ex2_state_mach <= execute_put2;
163	data_to_ram<=switch_port_out_data;
164	rd_ok<='1';
165	n<="0000";
166	delai:=0;
167	else
168	ex2_state_mach <= execute_put1;
169	end if;
170	when execute_put2 => if unsigned( packet_length) > 1 then
171
172	if switch_data_available = '1' and dma_wr_grant='1' then
173
174	packet_length <= packet_length - 1;
175	dest_address <= dest_address + 1;
176	ex2_state_mach <= execute_put2;
177	rd_ok<='1';
178	wr_ok<='1';
179	data_to_ram<=switch_port_out_data;
180	else
181	if switch_data_available = '1' and dma_wr_grant='0' then
182	if delai=0 then
183	data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch
184	end if;
185	delai:=1;--indique qu'un temps supplémentaire est
186	--nécessaire pour écrire la donnée en RAM
187	end if;
188	ex2_state_mach <= execute_put2;
189	rd_ok<='0'; --bloaque la lecture du switch pour ne pas perdre les données
190	end if;
191	else
192	if switch_data_available = '1' then
193	--la dernière donnée à écrire en RAM
194	data_to_ram<=switch_port_out_data;
195	rd_ok<='0';
196	wr_ok<='1';
197	else
198	rd_ok<='1';
199	wr_ok<='0';
200	end if;
201	if dma_wr_grant='1' then
202
203	ex2_state_mach <= execute_put3;
204	Wr_ok<='0';
205
206	end if;
207	end if;
208
209	when execute_put3 => if dma_rd_grant='1' then
210	dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
211	ex2_state_mach <= execute_put4;
212	n<="0000";
213	rd_ok<='1';
214	wr_ok<='0';
215	end if;
216
217	when execute_put4 => if n <=4 then
218
219	dma_wr<='1'; --demander un accès exclusif au bus
220	dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
221	else
222	dma_wr<='0';
223	dma_rd<='0';
224	end if;
225	if n=0 then
226	if dma_rd_grant='1' then
227	n<=n+1;
228	else
229	rd_ok<='1';
230	wr_ok<='0';
231	end if;
232	elsif n=1 then
233	if dma_rd_grant='1' then
234	n<=n+1;
235	else
236	rd_ok<='1';
237	wr_ok<='0';
238	end if;
239	elsif n=2 then
240	if dma_rd_grant='1' then
241	n<=n+1;
242	tempval:=Ram_data_in;
243	tempval(4):='1'; --SET du bit DReceived
244	data_to_ram<=tempval;
245	rd_ok<='0';
246	wr_ok<='1';
247	else
248	rd_ok<='1';
249	wr_ok<='0';
250	n<=n-1;
251	end if;
252	elsif n=3 then
253	if dma_wr_grant='1' then
254	rd_ok<='0';
255	wr_ok<='1';
256	n<=n+1;
257	end if;
258	elsif n=4 then
259	if dma_wr_grant='1' then
260	rd_ok<='0';
261	wr_ok<='1';
262	ex2_state_mach <= execute_put5;
263	n<="0000";
264	end if;
265	end if;
266
267
268
269	dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction
270	when execute_put5 =>
271	ex2_state_mach <= fetch_packet_type; -- fin du mpi_put
272
273
274	when execute_get1 => if switch_data_available = '1' then -- conversion du get en put en empilement dans le fifo
275	data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);
276	packet_length <= packet_length - 1;
277	ex2_state_mach <= execute_get2;
278	wr_ok<='1';
279	end if;
280	when execute_get2 => if fifo_full = '0' and switch_data_available ='1' and packet_length > 0 then
281	data_to_write_fifo <= switch_port_out_data;
282	packet_length <= packet_length - 1;
283	ex2_state_mach <= execute_get2;
284	wr_ok<='1';
285	elsif packet_length = 0 and switch_data_available ='1' then--
286	ex2_state_mach <= fetch_packet_type;
287	wr_ok<='0';
288	else
289	ex2_state_mach <= execute_get3;
290	wr_ok<='0';
291	end if;
292	when execute_get3 => if dma_rd_grant='1' then -- fin du mpi_put
293	ex2_state_mach <= execute_get4;
294	n<="0000";
295	--activer le bit sending du registre de transfert
296	else
297	ex2_state_mach <= execute_get3;
298	end if;
299
300	dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
301	when execute_get4 => if n <4 then
302
303	dma_wr<='1'; --demander un accès exclusif au bus
304	dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
305	else
306	dma_wr<='0';
307	dma_rd<='0';
308	end if;
309	if n=0 then
310	if dma_rd_grant='1' then
311	n<=n+1;
312
313	end if;
314	rd_ok<='1';
315	wr_ok<='0';
316	elsif n=1 then
317	if dma_rd_grant='1' then
318	n<=n+1;
319
320	end if;
321	rd_ok<='1';
322	wr_ok<='0';
323
324	elsif n=2 then
325	if dma_rd_grant='1' and dma_wr_grant='1' then
326	n<=n+1;
327	tempval:=Ram_data_in;
328	tempval(2):='1'; --mise à 1 du Bit Dreceiving
329	--tempval(5):='0'; --Mise à 0 du Bit Sent
330	data_to_ram<=tempval;
331	rd_ok<='0';
332	wr_ok<='1';
333	else
334	rd_ok<='1';
335	wr_ok<='0';
336	end if;
337
338	elsif n=3 then
339	if dma_wr_grant = '1' then
340	n<=n+1;
341	rd_ok<='0';
342	wr_ok<='1';
343	end if;
344	elsif n=4 then
345	if dma_wr_grant = '1' then
346	n<="0000";
347	ex2_state_mach <= fetch_packet_type; -- fin du mpi_get
348	else
349	rd_ok<='0';
350	wr_ok<='1';
351	--n<=n-1;
352	end if;
353	end if;
354
355
356	dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
357	-- execution du barrier
358	when execute_barrier1 => if switch_data_available = '1' then
359	pading_data <= switch_port_out_data;
360	ex2_state_mach <= execute_barrier2;
361	else
362	ex2_state_mach <= execute_barrier1;
363	end if;
364	when execute_barrier2 => if packet_type = MPI_BARRIER_REACHED then
365	barrier_counter <= barrier_counter + 1;
366	ex2_state_mach <= execute_barrier4;
367	else
368	ex2_state_mach <= execute_barrier3;
369	end if;
370	when execute_barrier3 => if n < 10 then
371	n <= n + 1;
372	ex2_state_mach <= execute_barrier3;
373	else
374	ex2_state_mach <= fetch_packet_type;
375	end if;
376	when execute_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED
377	data_to_write_fifo <= MPI_BARRIER_COMPLETED & "0000";
378	ex2_state_mach <= execute_barrier5;
379	else
380	ex2_state_mach <= fetch_packet_type;
381	end if;
382	when execute_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED
383	data_to_write_fifo <= "00000011";
384	ex2_state_mach <= execute_barrier6;
385	else
386	ex2_state_mach <= execute_barrier5;
387	end if;
388	when execute_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED
389	data_to_write_fifo <= "00000000";
390	ex2_state_mach <= execute_barrier7;
391	else
392	ex2_state_mach <= execute_barrier6;
393	end if;
394	when execute_barrier7 => if fifo_full = '0' then
395	barrier_counter <= "0000";
396	ex2_state_mach <= fetch_packet_type;
397	else
398	ex2_state_mach <= execute_barrier7;
399	end if;
400
401	when others => ex2_state_mach <= fetch_packet_type;
402	end case;
403	end if;
404	end if;
405	end process;
406
407	-- sortie de la machine à etat
408	--
409	ex2_fsm_action : process(ex2_state_mach, fifo_full, packet_length, data_to_write_fifo, packet_type,
410	switch_data_available,switch_port_out_data,Ram_data_in,rd_ok)
411	variable transact : std_logic_vector(Word-1 downto 0);
412	begin
413	-- code fonctionnel
414	case ex2_state_mach is
415
416	when fetch_packet_type => fifo_wr_en <= '0';
417	switch_port_out_rd_en <= switch_data_available;
418	packet_received <= '0';
419	dma_wr_request <= '0';
420	dma_rd_request <= '0';
421	barrier_completed <= '0';
422	Ram_data_out<=(others=>'Z');
423	Ram_rd<='0';
424	Ram_wr<='0';
425	Ready<='1';
426	AppInitReq<='0';
427
428
429	when decode_packet_type => fifo_wr_en <= '0';
430	switch_port_out_rd_en <= switch_data_available;
431	packet_received <= '0';
432	dma_wr_request <= '0';
433	dma_rd_request <= '0';
434	Ram_rd<='0';
435	Ram_wr<='0';
436	Ram_data_out<=(others=>'Z');
437	barrier_completed <= '0';
438	AppInitReq<='0';
439	Ready<='0';
440
441	when decode_packet_type2 => fifo_wr_en <= '0';
442	switch_port_out_rd_en <= '0';
443	packet_received <= '0';
444	dma_wr_request <= '0';
445	dma_rd_request <= '0';
446	Ram_rd<='0';
447	Ram_wr<='0';
448	Ram_data_out<=(others=>'Z');
449	barrier_completed <= '0';
450	AppInitReq<='0';
451	Ready<='0';
452	when fetch_addresses => fifo_wr_en <= '0';
453	switch_port_out_rd_en <= switch_data_available;
454	packet_received <= '0';
455	dma_wr_request <= '0';
456	dma_rd_request <= '0';
457	Ram_rd<='0';
458	Ram_wr<='0';
459	Ram_data_out<=(others=>'Z');
460	barrier_completed <= '0';
461	AppInitReq<='0';
462	Ready<='0';
463
464	when execute_put1 => fifo_wr_en <= '0';
465	switch_port_out_rd_en <= '0';
466	packet_received <= '0';
467	dma_wr_request <= '1';
468	dma_rd_request <= '0';
469	Ram_rd<='0';
470	Ram_wr<='0';
471	Ram_data_out<=(others=>'Z');
472	barrier_completed <= '0';
473	AppInitReq<='0';
474	Ready<='0';
475
476	when execute_put2 => Ready<='0';
477	fifo_wr_en <= '0';
478	switch_port_out_rd_en <=rd_ok;
479
480	if rd_ok = '1' then
481
482	Ram_data_out<=switch_port_out_data;
483	else
484	Ram_data_out<=data_to_ram;
485	end if;
486	Ram_wr<='1';
487	Ram_rd<='0';
488	packet_received <= '0';
489	dma_rd_request <= '0';
490	dma_wr_request <= '1';
491	AppInitReq<='0';
492	barrier_completed <= '0';
493	when execute_put3 => Ready<='0';
494	fifo_wr_en <= '0';
495	switch_port_out_rd_en <=rd_ok;
496	--ne pas corrompre le contenu de la RAM
497	--Ram_data_out<=data_to_ram;
498	Ram_wr<='0';
499	Ram_rd<='1';
500	packet_received <= '0';
501	dma_rd_request <= '1';
502	dma_wr_request <= '0';
503	AppInitReq<='0';
504	barrier_completed <= '0';
505
506
507	when execute_put4 => fifo_wr_en <= '0';
508	Ready<='0';
509	switch_port_out_rd_en <= '0';
510	packet_received <= '1';
511	dma_rd_request <= dma_rd;
512	dma_wr_request <=dma_wr;
513	Ram_wr<=wr_ok;
514	Ram_rd<=rd_ok;
515	AppInitReq<='0';
516	barrier_completed <= '0';
517	Ram_data_out<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution
518
519	when execute_put5 =>
520	Ready<='0';
521	switch_port_out_rd_en<='0';
522	fifo_wr_en <= '0';
523	packet_received <= '1';
524	AppInitReq<='0';
525	barrier_completed <= '0';
526	dma_rd_request <= dma_rd;
527	dma_wr_request <= dma_wr;
528	Ram_rd<=rd_ok;
529	Ram_wr<=wr_ok;
530	Ram_data_out<=data_to_ram;
531	--Result <=(1=>'1',others=>'0'); --put completed
532
533	when execute_get1=> fifo_wr_en <= '0';
534	switch_port_out_rd_en <= switch_data_available;
535	packet_received <= '0';
536	dma_wr_request <= '0';
537	dma_rd_request <= '0';
538	Ram_rd<='0';
539	Ram_wr<='0';
540	Ram_data_out<=(others=>'Z');
541	barrier_completed <= '0';
542	AppInitReq<='0';
543	Ready<='0';
544
545	when execute_get2 => if fifo_full = '0' and switch_data_available = '1' and packet_length > 0 then
546
547	switch_port_out_rd_en <='1';
548	else
549
550	switch_port_out_rd_en <='0';
551	end if;
552
553	fifo_wr_en <= Wr_ok;
554	Ready<='0';
555	packet_received <= '0';
556	dma_rd_request <= '0';
557	dma_wr_request <= '0';
558	Ram_rd<='0';
559	Ram_wr<='0';
560	Ram_data_out<=(others=>'Z');
561	barrier_completed <= '0';
562	AppInitReq<='0';
563
564	when execute_get3 => fifo_wr_en <= '0';
565	Ready<='0';
566	switch_port_out_rd_en <= '0';
567	packet_received <= '1';
568	dma_rd_request <= '1';
569	dma_wr_request <='0';
570	Ram_wr<='0';
571	Ram_rd<='1';
572	AppInitReq<='0';
573	barrier_completed <= '0';
574	--Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending
575
576	when execute_get4 =>
577	Ready<='0';
578	barrier_completed <= '0';
579	switch_port_out_rd_en<='0';
580	fifo_wr_en <= '0';
581	packet_received <= '1';
582	AppInitReq<='0';
583	dma_rd_request <= dma_rd;
584	dma_wr_request <= dma_wr;
585	Ram_rd<=rd_ok;
586	Ram_wr<=wr_ok;
587	Ram_data_out<=data_to_ram; --activer le bit DSending
588
589
590	when execute_barrier1 => fifo_wr_en <= '0';
591	switch_port_out_rd_en <= switch_data_available;
592	packet_received <= '0';
593	dma_wr_request <= '0';
594	dma_rd_request <= '0';
595	Ram_rd<='0';
596	Ram_wr<='0';
597	Ram_data_out<=(others=>'Z');
598	barrier_completed <= '0';
599	Ready<='0';
600	AppInitReq<='0';
601
602	when execute_barrier2 => fifo_wr_en <= '0';
603	Ready<='0';
604	switch_port_out_rd_en <='0';
605	packet_received <= '0';
606	dma_wr_request <= '0';
607	dma_rd_request <= '0';
608	Ram_rd<='0';
609	Ram_wr<='0';
610	Ram_data_out<=(others=>'Z');
611	barrier_completed <= '0';
612	AppInitReq<='0';
613
614	when execute_barrier3 => fifo_wr_en <= '0';
615	switch_port_out_rd_en <='0';
616	Ready<='0';
617	packet_received <= '0';
618	dma_wr_request <= '0';
619	dma_rd_request <= '0';
620	Ram_rd<='0';
621	Ram_wr<='0';
622	Ram_data_out<=(others=>'Z');
623	barrier_completed <= '1';
624	AppInitReq<='0';
625
626	when execute_barrier4 => fifo_wr_en <= '0';
627	switch_port_out_rd_en <='0';
628	packet_received <= '0';
629	dma_wr_request <= '0';
630	dma_rd_request <= '0';
631	Ram_rd<='0';
632	Ram_wr<='0';
633	Ram_data_out<=(others=>'Z');
634	barrier_completed <= '0';
635	AppInitReq<='0';
636	Ready<='0';
637
638
639	when execute_barrier5 => fifo_wr_en <= not(fifo_full);
640	switch_port_out_rd_en <='0';
641	packet_received <= '0';
642	dma_wr_request <= '0';
643	dma_rd_request <= '0';
644	Ram_rd<='0';
645	Ram_wr<='0';
646	Ram_data_out<=(others=>'Z');
647	barrier_completed <= '0';
648	AppInitReq<='0';
649	Ready<='0';
650
651	when execute_barrier6 => fifo_wr_en <= not(fifo_full);
652	switch_port_out_rd_en <= '0';
653	packet_received <= '0';
654	dma_wr_request <= '0';
655	dma_rd_request <= '0';
656	Ram_rd<='0';
657	Ram_wr<='0';
658	Ram_data_out<=(others=>'Z');
659	barrier_completed <= '0';
660	AppInitReq<='0';
661	Ready<='0';
662
663	when execute_barrier7 => fifo_wr_en <= not(fifo_full);
664	switch_port_out_rd_en <= '0';
665	packet_received <= '0';
666	dma_wr_request <= '0';
667	dma_rd_request <= '0';
668	Ram_rd<='0';
669	Ram_wr<='0';
670	Ram_data_out<=(others=>'Z');
671	barrier_completed <= '0';
672	AppInitReq<='0';
673	Ready<='0';
674
675
676	when execute_init1 => fifo_wr_en <= not(fifo_full);
677	switch_port_out_rd_en <= '0';
678	packet_received <= '0';
679	dma_wr_request <= '0';
680	dma_rd_request <= '0';
681	Ram_rd<='0';
682	Ram_wr<='0';
683	barrier_completed <= '0';
684	Ready<='0';
685	Ram_data_out<=(others =>'Z');
686	AppInitReq<='1';
687
688
689	when execute_init2 => fifo_wr_en <= not(fifo_full);
690	switch_port_out_rd_en <= '0';
691	packet_received <= '0';
692	dma_wr_request <= '0';
693	dma_rd_request <= '0';
694	Ram_rd<='0';
695	Ram_wr<='0';
696	barrier_completed <= '0';
697	Ram_data_out<=(others =>'Z');
698	AppInitReq<='1';
699	Ready<='0';
700
701	when others => Ready<='1'; -- le module est à nouveau libre
702	fifo_wr_en <= '0';
703	switch_port_out_rd_en <= '0';
704	packet_received <= '0';
705	dma_wr_request <= '0';
706	dma_rd_request <= '0';
707	barrier_completed <= '0';
708	Ram_data_out<=(others=>'Z');
709	Ram_rd<='0';
710	Ram_wr<='0';
711	Ready<='1';
712	AppInitReq<='0';
713	end case;
714
715	end process;
716
717	end Behavioral;
718

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source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhd @ 39

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