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Changeset 39 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhd
- Timestamp:
- Dec 7, 2012, 11:31:34 AM (12 years ago)
- File:
-
- 1 edited
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PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhd
r15 r39 91 91 signal data_to_write_fifo : std_logic_vector(Word-1 downto 0); 92 92 signal Ex2_on : std_logic:='0'; 93 signal rd_ok ,wr_ok:std_logic:='0';93 signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; 94 94 95 95 begin … … 169 169 end if; 170 170 when execute_put2 => if unsigned( packet_length) > 1 then 171 171 172 if switch_data_available = '1' and dma_wr_grant='1' then 172 -- n<=n+1; 173 --if delai=0 then 173 174 174 packet_length <= packet_length - 1; 175 175 dest_address <= dest_address + 1; 176 176 ex2_state_mach <= execute_put2; 177 177 rd_ok<='1'; 178 wr_ok<='1'; 178 179 data_to_ram<=switch_port_out_data; 179 --else 180 -- delai:=0; 181 -- end if; 182 else 183 if switch_data_available = '1' and dma_wr_grant='0'then 180 else 181 if switch_data_available = '1' and dma_wr_grant='0' then 184 182 if delai=0 then 185 data_to_ram<=switch_port_out_data; 183 data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch 186 184 end if; 187 185 delai:=1;--indique qu'un temps supplémentaire est … … 189 187 end if; 190 188 ex2_state_mach <= execute_put2; 191 rd_ok<='0'; 192 189 rd_ok<='0'; --bloaque la lecture du switch pour ne pas perdre les données 190 end if; 193 191 else 194 192 if switch_data_available = '1' then 195 193 --la dernière donnée à écrire en RAM 196 194 data_to_ram<=switch_port_out_data; 195 rd_ok<='0'; 196 wr_ok<='1'; 197 else 198 rd_ok<='1'; 199 wr_ok<='0'; 197 200 end if; 198 rd_ok<='0';199 200 201 if dma_wr_grant='1' then 201 202 202 203 ex2_state_mach <= execute_put3; 203 204 Wr_ok<='0'; 204 205 205 206 end if; … … 214 215 end if; 215 216 216 when execute_put4 => if n=0 then 217 when execute_put4 => if n <=4 then 218 219 dma_wr<='1'; --demander un accès exclusif au bus 220 dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données 221 else 222 dma_wr<='0'; 223 dma_rd<='0'; 224 end if; 225 if n=0 then 217 226 if dma_rd_grant='1' then 218 227 n<=n+1; 219 tempval:=Ram_data_in; 220 tempval(4):='1'; --SET du bit DReceived 221 data_to_ram<=tempval; 222 228 else 229 rd_ok<='1'; 230 wr_ok<='0'; 223 231 end if; 232 elsif n=1 then 233 if dma_rd_grant='1' then 234 n<=n+1; 235 else 224 236 rd_ok<='1'; 225 237 wr_ok<='0'; 226 elsif n=1 then 227 rd_ok<='0'; 228 wr_ok<='1'; 229 n<=n+1; 238 end if; 230 239 elsif n=2 then 240 if dma_rd_grant='1' then 241 n<=n+1; 242 tempval:=Ram_data_in; 243 tempval(4):='1'; --SET du bit DReceived 244 data_to_ram<=tempval; 245 rd_ok<='0'; 246 wr_ok<='1'; 247 else 248 rd_ok<='1'; 249 wr_ok<='0'; 250 n<=n-1; 251 end if; 252 elsif n=3 then 253 if dma_wr_grant='1' then 254 rd_ok<='0'; 255 wr_ok<='1'; 256 n<=n+1; 257 end if; 258 elsif n=4 then 231 259 if dma_wr_grant='1' then 232 260 rd_ok<='0'; … … 250 278 wr_ok<='1'; 251 279 end if; 252 when execute_get2 => if fifo_full = '0' and switch_data_available ='1' and packet_length > 0 then280 when execute_get2 => if fifo_full = '0' and switch_data_available ='1' and packet_length > 0 then 253 281 data_to_write_fifo <= switch_port_out_data; 254 282 packet_length <= packet_length - 1; … … 271 299 272 300 dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); 273 when execute_get4 => 301 when execute_get4 => if n <4 then 302 303 dma_wr<='1'; --demander un accès exclusif au bus 304 dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données 305 else 306 dma_wr<='0'; 307 dma_rd<='0'; 308 end if; 274 309 if n=0 then 275 if dma_rd_grant='1' then 310 if dma_rd_grant='1' then 311 n<=n+1; 312 313 end if; 314 rd_ok<='1'; 315 wr_ok<='0'; 316 elsif n=1 then 317 if dma_rd_grant='1' then 318 n<=n+1; 319 320 end if; 321 rd_ok<='1'; 322 wr_ok<='0'; 323 324 elsif n=2 then 325 if dma_rd_grant='1' and dma_wr_grant='1' then 276 326 n<=n+1; 277 327 tempval:=Ram_data_in; 278 328 tempval(2):='1'; --mise à 1 du Bit Dreceiving 279 tempval(5):='0'; --Mise à 0 du Bit Sent329 --tempval(5):='0'; --Mise à 0 du Bit Sent 280 330 data_to_ram<=tempval; 281 end if; 331 rd_ok<='0'; 332 wr_ok<='1'; 333 else 282 334 rd_ok<='1'; 283 335 wr_ok<='0'; 284 elsif n=1 then 285 n<=n+1; 286 elsif n=2 then 336 end if; 337 338 elsif n=3 then 339 if dma_wr_grant = '1' then 287 340 n<=n+1; 288 341 rd_ok<='0'; 289 342 wr_ok<='1'; 290 elsif n=3 then 343 end if; 344 elsif n=4 then 291 345 if dma_wr_grant = '1' then 292 346 n<="0000"; 293 347 ex2_state_mach <= fetch_packet_type; -- fin du mpi_get 294 end if; 295 rd_ok<='0'; 296 wr_ok<='1'; 348 else 349 rd_ok<='0'; 350 wr_ok<='1'; 351 --n<=n-1; 352 end if; 297 353 end if; 298 354 … … 439 495 switch_port_out_rd_en <=rd_ok; 440 496 --ne pas corrompre le contenu de la RAM 441 Ram_data_out<=data_to_ram;497 --Ram_data_out<=data_to_ram; 442 498 Ram_wr<='0'; 443 499 Ram_rd<='1'; … … 453 509 switch_port_out_rd_en <= '0'; 454 510 packet_received <= '1'; 455 dma_rd_request <= rd_ok;456 dma_wr_request <= wr_ok;511 dma_rd_request <= dma_rd; 512 dma_wr_request <=dma_wr; 457 513 Ram_wr<=wr_ok; 458 514 Ram_rd<=rd_ok; 459 515 AppInitReq<='0'; 460 516 barrier_completed <= '0'; 461 Ram_data_out<= Ram_data_in or "00000010"; -- le résultat de l'exécution517 Ram_data_out<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution 462 518 463 519 when execute_put5 => … … 468 524 AppInitReq<='0'; 469 525 barrier_completed <= '0'; 470 dma_rd_request <= rd_ok;471 dma_wr_request <= wr_ok;526 dma_rd_request <= dma_rd; 527 dma_wr_request <= dma_wr; 472 528 Ram_rd<=rd_ok; 473 529 Ram_wr<=wr_ok; 474 Ram_data_out<= ram_data_in or "00000010";530 Ram_data_out<=data_to_ram; 475 531 --Result <=(1=>'1',others=>'0'); --put completed 476 532 … … 516 572 AppInitReq<='0'; 517 573 barrier_completed <= '0'; 518 Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending574 --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending 519 575 520 576 when execute_get4 => … … 525 581 packet_received <= '1'; 526 582 AppInitReq<='0'; 527 dma_rd_request <= rd_ok;528 dma_wr_request <= wr_ok;583 dma_rd_request <= dma_rd; 584 dma_wr_request <= dma_wr; 529 585 Ram_rd<=rd_ok; 530 586 Ram_wr<=wr_ok; 531 Ram_data_out<= ram_data_in or "00000010"; --activer le bit DSending587 Ram_data_out<=data_to_ram; --activer le bit DSending 532 588 533 589
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