[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 12:16:03 06/13/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: MPI_CORE_SCHEDULER - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 24 | |
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| 25 | ---- Uncomment the following library declaration if instantiating |
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| 26 | ---- any Xilinx primitives in this code. |
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| 27 | --library UNISIM; |
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| 28 | --use UNISIM.VComponents.all; |
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| 29 | |
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| 30 | entity MPI_CORE_SCHEDULER is |
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| 31 | Port ( clk : in STD_LOGIC; |
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| 32 | reset : in STD_LOGIC; |
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| 33 | priority_rotation : in STD_LOGIC; |
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| 34 | instruction_fifo_empty : in STD_LOGIC; |
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| 35 | instruction_fifo_data : in STD_LOGIC_VECTOR (7 downto 0); |
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| 36 | instruction_available : out STD_LOGIC; |
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| 37 | |
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| 38 | get_request_fifo_data : in STD_LOGIC_VECTOR (7 downto 0); |
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| 39 | get_request_fifo_empty : in STD_LOGIC; |
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| 40 | instruction_fifo_rd_en : out STD_LOGIC; |
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| 41 | get_request_fifo_rd_en : out STD_LOGIC; |
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| 42 | |
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| 43 | fifo_selected : out STD_LOGIC; |
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| 44 | fifo_empty : out STD_LOGIC; |
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| 45 | fifo_rd_en : in STD_LOGIC; |
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| 46 | data_out : out STD_LOGIC_VECTOR (7 downto 0) |
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| 47 | ); |
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| 48 | end MPI_CORE_SCHEDULER; |
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| 49 | |
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| 50 | architecture Behavioral of MPI_CORE_SCHEDULER is |
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| 51 | |
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| 52 | signal sel_signal : std_logic; |
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| 53 | -- declaration des composants du scheduler |
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[41] | 54 | COMPONENT CDEMUX1 |
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[15] | 55 | PORT( |
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| 56 | di : IN std_logic; |
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| 57 | sel : IN std_logic; |
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| 58 | do1 : OUT std_logic; |
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| 59 | do2 : OUT std_logic |
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| 60 | ); |
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| 61 | END COMPONENT; |
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| 62 | |
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[41] | 63 | COMPONENT CMUXP1 |
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[15] | 64 | PORT( |
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| 65 | di1 : IN std_logic; |
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| 66 | di2 : IN std_logic; |
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| 67 | sel : IN std_logic; |
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| 68 | do : OUT std_logic |
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| 69 | ); |
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| 70 | END COMPONENT; |
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| 71 | |
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[41] | 72 | COMPONENT CMUX8 |
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[15] | 73 | PORT( |
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| 74 | di1 : IN std_logic_vector(7 downto 0); |
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| 75 | di2 : IN std_logic_vector(7 downto 0); |
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| 76 | sel : IN std_logic; |
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| 77 | do : OUT std_logic_vector(7 downto 0) |
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| 78 | ); |
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| 79 | END COMPONENT; |
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| 80 | |
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| 81 | COMPONENT round_robbin_machine |
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| 82 | PORT( |
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| 83 | get_request_fifo_empty : IN std_logic; |
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| 84 | instruction_fifo_empty : IN std_logic; |
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| 85 | priority_rotation : IN std_logic; |
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| 86 | clk : IN std_logic; |
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| 87 | reset : IN std_logic; |
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| 88 | fifo_selected : OUT std_logic; |
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| 89 | instruction_available : OUT std_logic; |
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| 90 | mux_sel : OUT std_logic |
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| 91 | ); |
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| 92 | END COMPONENT; |
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| 93 | begin |
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| 94 | -- instances des composants |
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| 95 | |
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| 96 | |
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| 97 | mpi_core_rr_machine: round_robbin_machine PORT MAP( |
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| 98 | get_request_fifo_empty => get_request_fifo_empty, |
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| 99 | instruction_fifo_empty => instruction_fifo_empty, |
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| 100 | priority_rotation => priority_rotation , |
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| 101 | clk => clk, |
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| 102 | fifo_selected => fifo_selected, |
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| 103 | instruction_available => instruction_available , |
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| 104 | reset => reset, |
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| 105 | mux_sel => sel_signal |
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| 106 | ); |
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| 107 | |
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| 108 | |
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[41] | 109 | Fifo_empty_MUX: CMUXP1 PORT MAP( |
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[15] | 110 | di1 => instruction_fifo_empty , |
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| 111 | di2 => get_request_fifo_empty, |
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| 112 | do => fifo_empty, |
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| 113 | sel => sel_signal |
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| 114 | ); |
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| 115 | |
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| 116 | |
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| 117 | |
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[41] | 118 | rd_en_demux: CDEMUX1 PORT MAP( |
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[15] | 119 | di => fifo_rd_en , |
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| 120 | sel => sel_signal, |
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| 121 | do1 => instruction_fifo_rd_en, |
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| 122 | do2 => get_request_fifo_rd_en |
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| 123 | ); |
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| 124 | |
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[41] | 125 | data_MUX8: CMUX8 PORT MAP( |
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[15] | 126 | di1 => instruction_fifo_data , |
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| 127 | di2 => get_request_fifo_data, |
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| 128 | sel => sel_signal, |
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| 129 | do => data_out |
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| 130 | ); |
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| 131 | |
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| 132 | |
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| 133 | |
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| 134 | end Behavioral; |
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| 135 | |
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