Changeset 41 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhd

Timestamp:

Dec 20, 2012, 3:42:20 PM (12 years ago)

Author:

rolagamo

Message:

Ceci est la version stable avant optimisation

File:

• PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhd (modified) (6 diffs)

PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhd

@@ -52 +52 @@
 signal sel_signal : std_logic;
 -- declaration des composants du scheduler
-COMPONENT DEMUX1
+COMPONENT CDEMUX1
         PORT(
                 di : IN std_logic;
@@ -61 +61 @@
         END COMPONENT;
         
-COMPONENT MUX1
+COMPONENT CMUXP1
         PORT(
                 di1 : IN std_logic;
@@ -70 +70 @@
         END COMPONENT;
 
-COMPONENT MUX8
+COMPONENT CMUX8
         PORT(
                 di1 : IN std_logic_vector(7 downto 0);
@@ -107 +107 @@
 
 
-Fifo_empty_MUX: MUX1 PORT MAP(
+Fifo_empty_MUX: CMUXP1 PORT MAP(
                 di1 => instruction_fifo_empty ,
                 di2 => get_request_fifo_empty,
@@ -116 +116 @@
         
 
-rd_en_demux: DEMUX1 PORT MAP(
+rd_en_demux: CDEMUX1 PORT MAP(
                 di => fifo_rd_en ,
                 sel => sel_signal,
@@ -123 +123 @@
         );
         
-data_MUX8: MUX8 PORT MAP(
+data_MUX8: CMUX8 PORT MAP(
                 di1 => instruction_fifo_data ,
                 di2 => get_request_fifo_data,