[15] | 1 | -------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM Roland Christian |
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| 4 | -- |
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| 5 | -- Create Date: 16:44:13 08/01/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: C:/Core MPI/CORE_MPI/MultiMPITest.vhd |
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| 8 | -- Project Name: MPI_CORE_COMPONENTS |
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| 9 | -- Target Device: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- VHDL Test Bench Created by ISE for module: MPI_NOC |
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| 14 | -- |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | -- |
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| 22 | -- |
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| 23 | -------------------------------------------------------------------------------- |
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| 24 | LIBRARY ieee; |
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| 25 | USE ieee.std_logic_1164.ALL; |
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| 26 | |
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| 27 | library NocLib ; |
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| 28 | |
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| 29 | use NocLib.CoreTypes.all; |
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| 30 | use work.Packet_type.all; |
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| 31 | |
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| 32 | USE ieee.numeric_std.ALL; |
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| 33 | |
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| 34 | ENTITY MultiMPITest IS |
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[41] | 35 | --simulation translate_off |
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| 36 | port (clkm : in std_logic; |
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| 37 | reset : in std_logic; |
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| 38 | result : out std_logic_vector(Word-1 downto 0)); |
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| 39 | --simulation translate_on |
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[15] | 40 | END MultiMPITest; |
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| 41 | |
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| 42 | ARCHITECTURE behavior OF MultiMPITest IS |
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| 43 | |
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| 44 | -- Component Declaration for the Unit Under Test (UUT) |
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| 45 | |
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| 46 | COMPONENT MPI_NOC |
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| 47 | generic (NPROC: natural:=2); |
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| 48 | PORT( |
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| 49 | MPI_Node_in : IN Ar_MPIPort_in(1 to NPROC); |
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| 50 | MPI_Node_Out : OUT Ar_MPIPort_out(1 to NPROC) |
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| 51 | ); |
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| 52 | END COMPONENT; |
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| 53 | Component PE |
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| 54 | generic(destid : natural); |
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| 55 | Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 56 | Instruction_en : out STD_LOGIC; |
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| 57 | Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 58 | clk : in STD_LOGIC; |
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| 59 | reset : in STD_LOGIC; |
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| 60 | Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 61 | Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 62 | Core_RAM_WE : in STD_LOGIC; |
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| 63 | Core_RAM_EN : in STD_LOGIC; |
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| 64 | --Core_RAM_ENB : in STD_LOGIC; |
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| 65 | Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 66 | Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 67 | Core_Hold_req : in STD_LOGIC; |
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| 68 | Core_Hold_Ack : out STD_LOGIC); |
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| 69 | end Component; |
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| 70 | |
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| 71 | constant clk_period : time := 10 ns; |
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[41] | 72 | constant PROC : positive :=8; |
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| 73 | -- synthesis translate_off |
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[15] | 74 | --===================signaux pour l'horloge ============================== |
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| 75 | signal reset,clkm : std_logic := '0'; |
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| 76 | --======================================================================== |
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[41] | 77 | -- synthesis translate_on |
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[15] | 78 | --signaux pour la gestion de la MAE |
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| 79 | type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, |
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| 80 | putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); |
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| 81 | signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées |
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| 82 | signal count,count_i : natural range 0 to 15:=0; |
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| 83 | |
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| 84 | signal MPI_Node_in : Ar_MPIPort_in(1 to PROC) ; |
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| 85 | signal MPI_Node_Out : Ar_MPIPort_out(1 to PROC); |
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| 86 | |
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| 87 | |
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| 88 | |
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| 89 | |
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| 90 | BEGIN |
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[41] | 91 | Xbar: MPI_NOC GENERIC MAP (NPROC=>PROC) |
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[15] | 92 | PORT MAP ( |
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| 93 | MPI_Node_in => MPI_Node_in, |
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| 94 | MPI_Node_Out => MPI_Node_Out |
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| 95 | ); |
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| 96 | |
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| 97 | PE1: PE generic map (DestId=>1) |
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| 98 | Port Map ( |
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| 99 | Instruction => MPi_Node_in(1).Instruction, |
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| 100 | Instruction_en => MPi_Node_in(1).Instruction_en, |
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| 101 | Core_PushOut => MPi_Node_out(1).PushOut, |
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| 102 | clk =>clkm, |
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| 103 | reset =>reset, |
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| 104 | Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out, |
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| 105 | Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in, |
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| 106 | Core_RAM_WE => MPI_Node_out(1).ram_we, |
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| 107 | Core_RAM_EN => MPI_Node_out(1).ram_en, |
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| 108 | -- Core_RAM_ENB => MPI_Node_out(1).ram_en, |
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| 109 | Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr, |
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| 110 | Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd, |
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| 111 | Core_Hold_req => MPI_Node_out(1).hold_req, |
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| 112 | Core_Hold_Ack => MPI_Node_in(1).hold_ack |
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| 113 | ); |
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| 114 | |
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| 115 | PE2: PE Generic map (DestId=>0) |
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| 116 | Port Map ( |
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| 117 | Instruction => MPi_Node_in(2).Instruction, |
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| 118 | Instruction_en => MPi_Node_in(2).Instruction_en, |
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| 119 | Core_PushOut => MPi_Node_out(2).PushOut, |
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| 120 | clk =>clkm, |
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| 121 | reset =>reset, |
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| 122 | Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out, |
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| 123 | Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in, |
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| 124 | Core_RAM_WE => MPI_Node_out(2).ram_we, |
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| 125 | Core_RAM_EN => MPI_Node_out(2).ram_en, |
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| 126 | --Core_RAM_ENB => MPI_Node_out(2).ram_en, |
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| 127 | Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr, |
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| 128 | Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd, |
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| 129 | Core_Hold_req => MPI_Node_out(2).hold_req, |
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| 130 | Core_Hold_Ack => MPI_Node_in(2).hold_ack |
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| 131 | ); |
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[41] | 132 | PE3: PE generic map (DestId=>2) |
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| 133 | Port Map ( |
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| 134 | Instruction => MPi_Node_in(3).Instruction, |
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| 135 | Instruction_en => MPi_Node_in(3).Instruction_en, |
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| 136 | Core_PushOut => MPi_Node_out(3).PushOut, |
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| 137 | clk =>clkm, |
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| 138 | reset =>reset, |
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| 139 | Core_RAM_Data_Out =>MPi_Node_in(3).Ram_Data_out, |
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| 140 | Core_RAM_Data_IN => MPI_Node_out(3).ram_data_in, |
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| 141 | Core_RAM_WE => MPI_Node_out(3).ram_we, |
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| 142 | Core_RAM_EN => MPI_Node_out(3).ram_en, |
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| 143 | -- Core_RAM_ENB => MPI_Node_out(1).ram_en, |
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| 144 | Core_RAM_Address_Wr => MPI_Node_out(3).ram_address_wr, |
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| 145 | Core_RAM_Address_Rd => MPI_Node_out(3).ram_address_rd, |
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| 146 | Core_Hold_req => MPI_Node_out(3).hold_req, |
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| 147 | Core_Hold_Ack => MPI_Node_in(3).hold_ack |
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| 148 | ); |
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| 149 | |
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| 150 | --PE4: PE Generic map (DestId=>3) |
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| 151 | -- Port Map ( |
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| 152 | -- Instruction => MPi_Node_in(4).Instruction, |
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| 153 | -- Instruction_en => MPi_Node_in(4).Instruction_en, |
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| 154 | -- Core_PushOut => MPi_Node_out(4).PushOut, |
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| 155 | -- clk =>clkm, |
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| 156 | -- reset =>reset, |
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| 157 | -- Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out, |
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| 158 | -- Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in, |
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| 159 | -- Core_RAM_WE => MPI_Node_out(4).ram_we, |
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| 160 | -- Core_RAM_EN => MPI_Node_out(4).ram_en, |
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| 161 | -- --Core_RAM_ENB => MPI_Node_out(2).ram_en, |
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| 162 | -- Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr, |
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| 163 | -- Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd, |
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| 164 | -- Core_Hold_req => MPI_Node_out(4).hold_req, |
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| 165 | -- Core_Hold_Ack => MPI_Node_in(4).hold_ack |
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| 166 | --); |
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[15] | 167 | MPI_Node_in(1).reset<=reset; |
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| 168 | MPI_Node_in(1).clk<=clkm; |
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| 169 | MPI_Node_in(2).reset<=reset; |
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| 170 | MPI_Node_in(2).clk<=clkm; |
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[41] | 171 | MPI_Node_in(3).reset<=reset; |
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| 172 | MPI_Node_in(3).clk<=clkm; |
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| 173 | MPI_Node_in(4).reset<=reset; |
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| 174 | MPI_Node_in(4).clk<=clkm; |
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| 175 | Result<=MPi_Node_out(1).PushOut; |
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[15] | 176 | --============================================================= |
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| 177 | -- Clock process definitions |
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| 178 | --============================================================= |
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[41] | 179 | -- synthesis translate_off |
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| 180 | clk_process :process |
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[15] | 181 | begin |
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| 182 | clkm <= '0' ; |
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| 183 | wait for clk_period/2; |
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| 184 | clkm <= '1' ; |
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| 185 | wait for clk_period/2; |
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| 186 | end process; |
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| 187 | stim_proc: process |
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| 188 | begin |
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| 189 | -- hold reset state for 100 ns. |
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| 190 | reset<='0'; |
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| 191 | wait for 1 ns; |
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| 192 | reset<='1'; |
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| 193 | wait for clk_period*10; |
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| 194 | reset<='0'; |
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| 195 | wait; |
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| 196 | |
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| 197 | |
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| 198 | end process; |
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[41] | 199 | -- synthesis translate_on |
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[15] | 200 | --================================================================ |
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| 201 | END; |
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