Changeset 41 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.vhd

Timestamp:

Dec 20, 2012, 3:42:20 PM (12 years ago)

Author:

rolagamo

Message:

Ceci est la version stable avant optimisation

File:

• PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.vhd (modified) (5 diffs)

PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.vhd

@@ -33 +33 @@
  
 ENTITY MultiMPITest IS
---port (clkm : in std_logic;
---reset : in std_logic;
---result : out std_logic_vector(Word-1 downto 0));
+--simulation translate_off
+port (clkm : in std_logic;
+reset : in std_logic;
+result : out std_logic_vector(Word-1 downto 0));
+--simulation translate_on
 END MultiMPITest;
  
@@ -68 +70 @@
  
         constant clk_period : time := 10 ns;
-   constant PROC : positive :=4;
+   constant PROC : positive :=8;
+-- synthesis translate_off
 --===================signaux pour l'horloge ==============================
 signal reset,clkm : std_logic := '0';
 --========================================================================
+-- synthesis translate_on
  --signaux pour la gestion de la MAE
  type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, 
@@ -85 +89 @@
  
 BEGIN
- uut: MPI_NOC GENERIC MAP (NPROC=>PROC)
+ Xbar: MPI_NOC GENERIC MAP (NPROC=>PROC)
                 PORT MAP (
           MPI_Node_in => MPI_Node_in,
@@ -126 +130 @@
            Core_Hold_Ack => MPI_Node_in(2).hold_ack
 );
+PE3: PE generic map (DestId=>2)
+Port Map (
+Instruction => MPi_Node_in(3).Instruction,
+           Instruction_en => MPi_Node_in(3).Instruction_en,
+                          Core_PushOut => MPi_Node_out(3).PushOut,
+           clk =>clkm,
+           reset =>reset,
+           Core_RAM_Data_Out =>MPi_Node_in(3).Ram_Data_out,
+           Core_RAM_Data_IN => MPI_Node_out(3).ram_data_in,
+           Core_RAM_WE => MPI_Node_out(3).ram_we,
+           Core_RAM_EN => MPI_Node_out(3).ram_en,
+          -- Core_RAM_ENB => MPI_Node_out(1).ram_en,
+           Core_RAM_Address_Wr => MPI_Node_out(3).ram_address_wr,
+           Core_RAM_Address_Rd => MPI_Node_out(3).ram_address_rd,
+           Core_Hold_req => MPI_Node_out(3).hold_req,
+           Core_Hold_Ack => MPI_Node_in(3).hold_ack
+);
+
+--PE4: PE       Generic map (DestId=>3)
+--                      Port Map (
+--                              Instruction => MPi_Node_in(4).Instruction,
+--           Instruction_en => MPi_Node_in(4).Instruction_en,
+--                        Core_PushOut => MPi_Node_out(4).PushOut,
+--           clk =>clkm,
+--           reset =>reset,
+--           Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out,
+--           Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in,
+--           Core_RAM_WE => MPI_Node_out(4).ram_we,
+--           Core_RAM_EN => MPI_Node_out(4).ram_en,
+--           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
+--           Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr,
+--           Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd,
+--           Core_Hold_req => MPI_Node_out(4).hold_req,
+--           Core_Hold_Ack => MPI_Node_in(4).hold_ack
+--);
 MPI_Node_in(1).reset<=reset;    
 MPI_Node_in(1).clk<=clkm;
 MPI_Node_in(2).reset<=reset;    
 MPI_Node_in(2).clk<=clkm;
---Result<=MPi_Node_out(1).PushOut;
+MPI_Node_in(3).reset<=reset;    
+MPI_Node_in(3).clk<=clkm;
+MPI_Node_in(4).reset<=reset;    
+MPI_Node_in(4).clk<=clkm;
+Result<=MPi_Node_out(1).PushOut;
 --=============================================================
    -- Clock process definitions
 --=============================================================
-   clk_process :process
+-- synthesis translate_off 
+ clk_process :process
    begin
                 clkm <= '0' ;
@@ -153 +197 @@
         
         end process;
+-- synthesis translate_on
 --================================================================
 END;