[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 21:20:54 07/16/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: PE - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | library NocLib ; |
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[39] | 23 | library Std; |
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[15] | 24 | --use IEEE.STD_LOGIC_ARITH.ALL; |
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| 25 | --use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 26 | use NocLib.CoreTypes.all; |
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| 27 | use work.Packet_type.all; |
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| 28 | use work.MPI_RMA.all; |
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[41] | 29 | -- synthesis translate_off |
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[39] | 30 | use std.textio.all; |
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[41] | 31 | -- synthesis translate_on |
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[15] | 32 | use IEEE.NUMERIC_STD.ALL; |
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| 33 | |
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| 34 | |
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| 35 | entity PE is |
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[41] | 36 | Generic (DestId : natural:=0 ); |
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[15] | 37 | Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 38 | Instruction_en : out STD_LOGIC; |
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| 39 | Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 40 | clk : in STD_LOGIC; |
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| 41 | reset : in STD_LOGIC; |
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| 42 | Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 43 | Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 44 | Core_RAM_WE : in STD_LOGIC; |
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| 45 | Core_RAM_EN : in STD_LOGIC; |
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| 46 | --Core_RAM_ENB : in STD_LOGIC; |
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| 47 | Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 48 | Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 49 | Core_Hold_req : in STD_LOGIC; |
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| 50 | Core_Hold_Ack : out STD_LOGIC); |
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| 51 | end PE; |
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| 52 | |
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| 53 | architecture Behavioral of PE is |
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| 54 | COMPONENT RAM_v |
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| 55 | generic (width : positive;size :positive); |
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| 56 | PORT( |
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| 57 | clka : IN std_logic; |
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| 58 | clkb : IN std_logic; |
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| 59 | wea : IN std_logic; |
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| 60 | ena : IN std_logic; |
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| 61 | enb : IN std_logic; |
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| 62 | addra : IN std_logic_vector; |
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| 63 | addrb : IN std_logic_vector; |
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| 64 | dia : IN std_logic_vector; |
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| 65 | dob : OUT std_logic_vector |
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| 66 | ); |
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| 67 | END COMPONENT; |
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| 68 | --données du programme PE |
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| 69 | --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 70 | signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0'; |
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| 71 | signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; |
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| 72 | signal pe_instr_en,pe_hold_ack: std_logic:='0'; |
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| 73 | signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 74 | signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 75 | signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); |
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| 76 | signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); |
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| 77 | signal sram : typ_dpram; |
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| 78 | |
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| 79 | signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); |
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| 80 | signal dpid,dpid_i : natural range 0 to 15:=DestId; |
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| 81 | signal MyRank :std_logic_vector(3 downto 0); |
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| 82 | signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque |
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| 83 | signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée |
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| 84 | signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO |
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| 85 | signal Lib_Init : std_logic; -- l'initialisation est terminée |
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| 86 | --signaux pour la gestion de la MAE |
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[39] | 87 | type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate, putdata,getdata,WinCompleted,finalize,st_timeout); |
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[15] | 88 | signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées |
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| 89 | signal count,count_i : natural range 0 to 15:=0; |
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| 90 | |
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| 91 | |
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| 92 | signal RunState : typ_mae; |
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| 93 | signal Ram_busy :std_logic:='0'; |
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| 94 | begin |
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| 95 | Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) |
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| 96 | PORT MAP( |
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| 97 | clka =>clk, |
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| 98 | clkb => clk, |
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| 99 | wea => ram_we, |
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| 100 | ena => ram_ena, |
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| 101 | enb => ram_enb, |
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| 102 | addra => ram_addra, |
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| 103 | addrb =>ram_addrb, |
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| 104 | dia => ram_din, |
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| 105 | dob => ram_do |
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| 106 | ); |
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| 107 | --================================================================ |
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| 108 | --MUX de la RAM |
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| 109 | |
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| 110 | Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr, |
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| 111 | Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do, |
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| 112 | Pe_ram_din,Pe_ram_we ) |
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| 113 | begin |
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| 114 | case ramsel is |
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| 115 | |
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| 116 | when '1' => |
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| 117 | ram_addra <= Core_ram_address_wr ; |
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| 118 | ram_addrb <= Core_ram_address_rd ; |
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| 119 | ram_ena <= Core_ram_en; |
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| 120 | ram_enb <= Core_ram_en; |
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| 121 | ram_we<= Core_ram_we; |
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| 122 | ram_din <= Core_ram_data_in; |
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| 123 | pe_ram_do<=(others=>'Z'); |
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| 124 | Core_ram_data_out<=ram_do; |
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| 125 | |
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| 126 | when others => |
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| 127 | ram_addra <= pe_ram_addra; |
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| 128 | ram_addrb <= pe_ram_addrb; |
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| 129 | ram_ena <= pe_ram_ena; |
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| 130 | ram_enb <= pe_ram_enb; |
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| 131 | ram_we<= pe_ram_we; |
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| 132 | ram_din <=pe_ram_din; |
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| 133 | Core_ram_data_out<=(others=>'Z'); |
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| 134 | pe_ram_do<=ram_do; |
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| 135 | end case ; |
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| 136 | end process ; |
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| 137 | |
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| 138 | |
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| 139 | |
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| 140 | Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --********A changer ********** |
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| 141 | --=== !!!!! attention la suppression de la ligne ci-dessous empêche ce |
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| 142 | -- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!! |
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| 143 | instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); |
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| 144 | |
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| 145 | dpid<=dpid_i; |
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| 146 | |
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| 147 | Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié |
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| 148 | Lib_init<=Core_Pushout(4); -- Initialized |
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| 149 | -- pe_hold_req<=Core_hold_req; |
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| 150 | --Core_hold_ack<=pe_hold_ack; |
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| 151 | |
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| 152 | hold:process (Core_Hold_Req,clk,reset) |
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| 153 | begin |
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| 154 | if rising_edge(clk) then |
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| 155 | if reset='1' then |
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| 156 | Core_Hold_Ack<='0'; |
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| 157 | else |
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| 158 | if Core_Hold_Req='1' then |
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| 159 | |
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| 160 | ramsel<=not(ram_busy); |
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| 161 | Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération |
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| 162 | Pe_hold_ack<=not(ram_busy); |
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| 163 | else |
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| 164 | Core_Hold_Ack<='0'; |
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| 165 | ramsel<='0'; |
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| 166 | Pe_hold_ack<='0'; |
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| 167 | |
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| 168 | end if; |
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| 169 | end if; |
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| 170 | end if; |
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| 171 | end process hold; |
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| 172 | --======================================================================= |
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| 173 | |
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| 174 | |
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| 175 | |
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| 176 | --======================================================================= |
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| 177 | --MAE du PE |
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| 178 | --======================================================================= |
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| 179 | |
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| 180 | pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do) |
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| 181 | |
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| 182 | constant DATAPTR : natural :=256; |
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| 183 | variable bfill,destrank,pid,mport : natural range 0 to 15; |
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| 184 | variable fsrc,ret : natural range 0 to 15:=0; |
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| 185 | variable timeout,ct,dlen : natural range 0 to 255; |
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| 186 | variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); |
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[39] | 187 | variable mywin : Mpi_win; |
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[15] | 188 | variable iack : std_logic:='0'; |
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| 189 | variable adresse,adresse_rd :natural range 0 to 65536; |
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| 190 | variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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[39] | 191 | --======================================================= |
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| 192 | --variables pour la création du fichier de résultats |
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[41] | 193 | -- synthesis translate_off |
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[39] | 194 | type char_file is file of character; |
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| 195 | file f: text; |
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| 196 | variable status :file_open_status ; |
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| 197 | variable char_count: integer range 0 to 65536 := 0; |
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| 198 | variable str: string (1 to 79) ; |
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| 199 | variable L: line; |
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| 200 | variable fopened: std_logic:='0'; |
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[41] | 201 | -- synthesis translate_on |
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[39] | 202 | --====================================================== |
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[15] | 203 | begin |
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| 204 | --=== Partie combinatoire du process =================================== |
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[41] | 205 | |
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[39] | 206 | --=== Fin de la partie combinatoire du process ========================== |
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| 207 | |
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| 208 | |
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| 209 | |
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| 210 | --end loop; |
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| 211 | |
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[15] | 212 | if (clk'event and clk='1') then |
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[41] | 213 | Libr.Instr_ack<=Core_pushout(0); |
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| 214 | Libr.InitOk<=Core_pushout(4); |
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| 215 | Libr.Hold_Req<=Core_Hold_req; |
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| 216 | Libr.Hold_Ack<=Pe_Hold_Ack; |
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| 217 | Libr.RamSel<=RamSel; |
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| 218 | sram.data_out<=PE_ram_do; |
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| 219 | |
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[15] | 220 | if reset='1' then |
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| 221 | RunState<=start; |
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| 222 | |
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| 223 | else |
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| 224 | |
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| 225 | Libr.Instr_ack<=Core_pushout(0); |
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| 226 | Libr.InitOk<=Core_pushout(4); |
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| 227 | Libr.Hold_Req<=Core_Hold_req; |
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| 228 | Libr.Hold_Ack<=Pe_Hold_Ack; |
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| 229 | Libr.RamSel<=RamSel; |
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| 230 | sram.data_out<=PE_ram_do; |
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| 231 | case RunState is |
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| 232 | when start => |
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| 233 | Dcount<=0; |
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| 234 | if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide |
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| 235 | RunState<=Fillmem; |
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| 236 | end if; |
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| 237 | Ram_busy<='0'; |
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| 238 | PE_Instr_En<='0'; |
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| 239 | iack:='0'; |
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| 240 | adresse:=DATAPTR; |
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| 241 | |
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| 242 | adresse_rd:=0; |
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| 243 | timeout:=0; |
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| 244 | dcount<=0; |
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[41] | 245 | -- synthesis translate_off |
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[39] | 246 | if fopened='0' then |
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| 247 | file_open(status,f, integer'image(destid) & "test_file0.txt", APPEND_MODE); |
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| 248 | --while not endfile(c_file_handle) loop |
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| 249 | --end if; |
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| 250 | |
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| 251 | --write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now))); |
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| 252 | --report l.all; |
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| 253 | -- writeline (f, l) ; |
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| 254 | fopened:='1'; |
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| 255 | end if; |
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[41] | 256 | -- synthesis translate_on |
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[15] | 257 | when Fillmem => |
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| 258 | if Ramsel='0' then |
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| 259 | |
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| 260 | |
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| 261 | |
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| 262 | PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; |
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| 263 | PE_Instr_En<='0'; |
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| 264 | dcount<=dcount+1; |
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| 265 | |
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[35] | 266 | if dcount=200 then |
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[15] | 267 | bfill:=bfill+1; |
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| 268 | |
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| 269 | if bfill=4 then |
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| 270 | RunState<=InitApp; |
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| 271 | else |
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| 272 | RunState<=nextfill; |
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| 273 | end if; |
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| 274 | else |
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| 275 | adresse:=adresse+1; |
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| 276 | RunState<=Fillmem; |
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| 277 | end if; |
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| 278 | else -- attente de la libéraion de la mémoire |
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| 279 | timeout:=timeout+1; |
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| 280 | if timeout=100 then |
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| 281 | RunState<=st_timeout; |
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| 282 | end if; |
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| 283 | |
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| 284 | end if; |
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| 285 | when nextfill => --prépare le prochain bloc mémoire qui sera rempli |
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[35] | 286 | adresse:=200*bfill; |
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[15] | 287 | dcount<=0; |
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| 288 | ct:=0; |
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| 289 | RunState<=Fillmem; |
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| 290 | PE_Instr_En<='0'; |
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| 291 | when InitApp => |
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| 292 | --code pour Init |
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[41] | 293 | dlen:=251; |
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[39] | 294 | if ct=0 then |
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[41] | 295 | -- synthesis translate_off |
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| 296 | write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & time'image(now))); |
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[39] | 297 | |
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| 298 | report l.all; |
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| 299 | writeline (f, l) ; |
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[41] | 300 | -- synthesis translate_on |
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[39] | 301 | end if; |
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[15] | 302 | pMPI_Init(ct,Libr,Clk,SRam); |
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| 303 | PE_Instr_EN<=Libr.instr_en; |
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| 304 | adresse:=to_integer(unsigned(sram.addr_wr)); |
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| 305 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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| 306 | PE_ram_din<=sram.data_in; |
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| 307 | |
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| 308 | --if Libr.InitOk='1' then |
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| 309 | if ct=0 then |
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[39] | 310 | RunState<=GetRank; |
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[41] | 311 | -- synthesis translate_off |
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| 312 | write (l,string'("Dlen; ;INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); |
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[39] | 313 | report l.all; |
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| 314 | writeline (f, l) ; |
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[41] | 315 | -- synthesis translate_on |
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[15] | 316 | end if; |
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| 317 | |
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| 318 | |
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| 319 | |
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[39] | 320 | when GetRank => |
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| 321 | if ct=0 then |
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[41] | 322 | -- synthesis translate_off |
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| 323 | write (l,string'("Dlen; ;Rank1 " & integer'image(Dlen) & "; ; started ; " & time'image(now))); |
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[39] | 324 | report l.all; |
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| 325 | writeline (f, l) ; |
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[41] | 326 | -- synthesis translate_on |
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[39] | 327 | end if; |
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[15] | 328 | pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); |
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[39] | 329 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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[15] | 330 | if ct=0 then |
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[39] | 331 | RunState<=PutData; |
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[41] | 332 | -- synthesis translate_off |
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| 333 | write (l,string'("Dlen; ;Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); |
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[39] | 334 | report l.all; |
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[41] | 335 | writeline (f, l) ; |
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| 336 | -- synthesis translate_on |
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[15] | 337 | end if; |
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[39] | 338 | |
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[15] | 339 | |
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[39] | 340 | when Wincreate => |
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| 341 | |
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| 342 | |
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[15] | 343 | when putdata => --construire le packet pour le Put |
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| 344 | |
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[39] | 345 | --dlen:=251; --- |
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| 346 | if ct=0 then |
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[41] | 347 | -- synthesis translate_off |
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| 348 | write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now))); |
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[39] | 349 | report l.all; |
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| 350 | writeline (f, l) ; |
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[41] | 351 | -- synthesis translate_on |
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[39] | 352 | end if; |
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[15] | 353 | if unsigned(MyRank) = 0 then |
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[41] | 354 | Destrank:=2; |
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| 355 | |
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| 356 | elsif unsigned(MyRank) = 1 then |
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| 357 | Destrank:=0; |
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| 358 | elsif unsigned(MyRank) = 2 then |
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| 359 | Destrank:=1; |
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| 360 | elsif unsigned(MyRank) = 3 then |
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| 361 | Destrank:=2; |
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[15] | 362 | else |
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| 363 | DestRank:=0; |
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| 364 | end if; |
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[39] | 365 | |
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[15] | 366 | SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); |
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| 367 | DestAdr:=X"2000"; |
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[41] | 368 | pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); |
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[15] | 369 | |
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| 370 | adresse:=to_integer(unsigned(sram.addr_wr)); |
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| 371 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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| 372 | PE_Instr_EN<=Libr.instr_en; |
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| 373 | PE_ram_din<=sram.data_in; |
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| 374 | dcount<=ct; |
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| 375 | |
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| 376 | if ct=0 then |
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| 377 | RunState<=GetData; |
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[41] | 378 | -- synthesis translate_off |
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[39] | 379 | report "Put of Process n°; " & image(MyRank) & "; ended at ; " & time'image(now); |
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[41] | 380 | write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & time'image(now))); |
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[39] | 381 | report l.all; |
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[41] | 382 | writeline (f, l) ; |
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| 383 | -- synthesis translate_on |
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[15] | 384 | end if; |
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[39] | 385 | |
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[15] | 386 | |
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| 387 | when getdata => --positionnement du mot de longueur des données |
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[39] | 388 | --dlen:=251; --- |
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| 389 | if ct=0 then |
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[41] | 390 | -- synthesis translate_off |
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| 391 | write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & time'image(now))); |
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[39] | 392 | report l.all; |
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| 393 | writeline (f, l) ; |
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[41] | 394 | -- synthesis translate_on |
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[39] | 395 | end if; |
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| 396 | |
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[35] | 397 | SrcAdr:=X"0120"; |
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| 398 | DestAdr:=X"4000"; |
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[41] | 399 | if unsigned(MyRank) /= 2 then |
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| 400 | pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); |
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| 401 | else |
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| 402 | RunState<=wincompleted; |
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| 403 | end if; |
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[15] | 404 | adresse:=to_integer(unsigned(sram.addr_wr)); |
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| 405 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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| 406 | PE_Instr_EN<=Libr.instr_en; |
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| 407 | PE_ram_din<=sram.data_in; |
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| 408 | dcount<=ct; |
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| 409 | |
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| 410 | if ct=0 then |
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[39] | 411 | RunState<=wincompleted; |
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[41] | 412 | -- synthesis translate_off |
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[39] | 413 | assert ct/=0 report "GET_END " & integer'image(destrank) |
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| 414 | severity Warning ; |
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[41] | 415 | write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); |
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[39] | 416 | report l.all; |
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| 417 | |
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[41] | 418 | writeline (f, l) ; |
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| 419 | -- synthesis translate_on |
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[15] | 420 | end if; |
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| 421 | |
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[39] | 422 | when WinCompleted => |
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| 423 | if ct=0 then |
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[41] | 424 | -- synthesis translate_off |
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| 425 | write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now))); |
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[39] | 426 | report l.all; |
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| 427 | writeline (f, l) ; |
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[41] | 428 | -- synthesis translate_on |
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[39] | 429 | end if; |
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| 430 | pMPI_Win_wait(ct,Libr,sram,MyWin ); |
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| 431 | adresse:=to_integer(unsigned(sram.addr_wr)); |
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| 432 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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| 433 | if ct=0 then |
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| 434 | RunState<=finalize; |
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[41] | 435 | -- synthesis translate_off |
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| 436 | write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); |
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[39] | 437 | report l.all; |
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| 438 | writeline (f, l) ; |
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[41] | 439 | -- synthesis translate_on |
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[39] | 440 | |
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| 441 | end if; |
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[15] | 442 | |
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| 443 | |
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[39] | 444 | when finalize => |
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| 445 | if ct=0 then |
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[41] | 446 | -- synthesis translate_off |
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| 447 | write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now))); |
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[39] | 448 | report l.all; |
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| 449 | writeline (f, l) ; |
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[41] | 450 | -- synthesis translate_on |
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[39] | 451 | end if; |
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| 452 | |
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| 453 | if ct=0 then |
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| 454 | RunState<=start; |
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[41] | 455 | -- synthesis translate_off |
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| 456 | write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); |
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[39] | 457 | report l.all; |
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| 458 | writeline (f, l) ; |
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| 459 | file_close(f); |
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[41] | 460 | -- synthesis translate_on |
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[39] | 461 | end if; |
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[15] | 462 | |
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| 463 | when st_timeout => |
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| 464 | |
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| 465 | --if ram_busy='1' then |
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| 466 | RunState<=start; |
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| 467 | --end if |
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| 468 | |
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| 469 | RunState<=start; |
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| 470 | end case; |
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| 471 | pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16)); |
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| 472 | pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16)); |
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| 473 | end if; |
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| 474 | end if; |
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| 475 | |
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| 476 | end process pPutGet; |
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| 477 | |
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| 478 | majPutGet:process (RunState,pe_ram_do,sram,Lib_Init) |
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| 479 | |
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| 480 | begin |
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| 481 | case RunState is |
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| 482 | when start => |
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| 483 | |
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| 484 | PE_Ram_we<='0'; |
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| 485 | PE_Ram_ena<='0'; |
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| 486 | PE_Ram_enb<='0'; |
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| 487 | --PE_Instr_En<='0'; |
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| 488 | |
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| 489 | when fillmem => |
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| 490 | PE_Ram_we<='1'; |
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| 491 | PE_Ram_ena<='1'; |
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| 492 | |
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| 493 | PE_Ram_enb<='0'; |
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| 494 | --PE_Instr_En<='0'; |
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| 495 | when nextfill => |
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| 496 | PE_Ram_we<='1'; |
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| 497 | PE_Ram_ena<='1'; |
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| 498 | PE_Ram_enb<='0'; |
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| 499 | |
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| 500 | when InitApp => |
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| 501 | -- PE_Ram_we<='1'; |
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| 502 | -- PE_Ram_ena<='1'; |
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| 503 | -- PE_Ram_enb<='0'; |
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| 504 | PE_Ram_we<=sram.we; |
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| 505 | PE_Ram_ena<=sram.ena; |
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| 506 | PE_Ram_enb<=sram.enb; |
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| 507 | |
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[39] | 508 | |
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| 509 | when GetRank => |
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[15] | 510 | |
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| 511 | PE_Ram_we<=sram.we; |
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| 512 | PE_Ram_ena<=sram.ena; |
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| 513 | PE_Ram_enb<=sram.enb; |
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[39] | 514 | when WinCreate => |
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[15] | 515 | |
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[39] | 516 | PE_Ram_we<=sram.we; |
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| 517 | PE_Ram_ena<=sram.ena; |
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| 518 | PE_Ram_enb<=sram.enb; |
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[15] | 519 | |
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| 520 | |
---|
[39] | 521 | --positionnement du mot de longueur des données |
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[15] | 522 | |
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| 523 | |
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[39] | 524 | when putdata => |
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[15] | 525 | srcadr0<=X"00"; |
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| 526 | srcadr1<=X"01"; |
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| 527 | destadr0<=X"00"; |
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| 528 | destadr1<=X"02"; |
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| 529 | PE_Ram_we<=sram.we; |
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| 530 | PE_Ram_ena<=sram.ena; |
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| 531 | PE_Ram_enb<=sram.enb; |
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[39] | 532 | |
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[15] | 533 | when getdata => |
---|
| 534 | PE_Ram_we<=sram.we; |
---|
| 535 | PE_Ram_ena<=sram.ena; |
---|
| 536 | PE_Ram_enb<=sram.enb; |
---|
| 537 | |
---|
[39] | 538 | when Wincompleted => |
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| 539 | PE_Ram_we<=sram.we; |
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| 540 | PE_Ram_ena<=sram.ena; |
---|
| 541 | PE_Ram_enb<=sram.enb; |
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[15] | 542 | |
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[39] | 543 | when finalize => |
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[15] | 544 | |
---|
| 545 | PE_Ram_we<='0'; |
---|
| 546 | PE_Ram_ena<='0'; |
---|
| 547 | PE_Ram_enb<='0'; |
---|
| 548 | |
---|
| 549 | |
---|
| 550 | when st_timeout => |
---|
| 551 | PE_Ram_we<='0'; |
---|
| 552 | PE_Ram_ena<='0'; |
---|
| 553 | PE_Ram_enb<='0'; |
---|
| 554 | |
---|
| 555 | |
---|
| 556 | end case; |
---|
| 557 | |
---|
| 558 | end process majPutGet ; |
---|
| 559 | end Behavioral; |
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| 560 | |
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