[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 21:20:54 07/16/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: PE - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | library NocLib ; |
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[39] | 23 | library Std; |
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[15] | 24 | --use IEEE.STD_LOGIC_ARITH.ALL; |
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| 25 | --use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 26 | use NocLib.CoreTypes.all; |
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| 27 | use work.Packet_type.all; |
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| 28 | use work.MPI_RMA.all; |
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[39] | 29 | use std.textio.all; |
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[15] | 30 | use IEEE.NUMERIC_STD.ALL; |
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| 31 | |
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| 32 | |
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| 33 | entity PE is |
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| 34 | Generic (DestId : natural ); |
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| 35 | Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 36 | Instruction_en : out STD_LOGIC; |
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| 37 | Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 38 | clk : in STD_LOGIC; |
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| 39 | reset : in STD_LOGIC; |
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| 40 | Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 41 | Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 42 | Core_RAM_WE : in STD_LOGIC; |
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| 43 | Core_RAM_EN : in STD_LOGIC; |
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| 44 | --Core_RAM_ENB : in STD_LOGIC; |
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| 45 | Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 46 | Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 47 | Core_Hold_req : in STD_LOGIC; |
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| 48 | Core_Hold_Ack : out STD_LOGIC); |
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| 49 | end PE; |
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| 50 | |
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| 51 | architecture Behavioral of PE is |
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| 52 | COMPONENT RAM_v |
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| 53 | generic (width : positive;size :positive); |
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| 54 | PORT( |
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| 55 | clka : IN std_logic; |
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| 56 | clkb : IN std_logic; |
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| 57 | wea : IN std_logic; |
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| 58 | ena : IN std_logic; |
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| 59 | enb : IN std_logic; |
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| 60 | addra : IN std_logic_vector; |
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| 61 | addrb : IN std_logic_vector; |
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| 62 | dia : IN std_logic_vector; |
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| 63 | dob : OUT std_logic_vector |
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| 64 | ); |
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| 65 | END COMPONENT; |
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| 66 | --données du programme PE |
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| 67 | --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 68 | signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0'; |
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| 69 | signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; |
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| 70 | signal pe_instr_en,pe_hold_ack: std_logic:='0'; |
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| 71 | signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 72 | signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 73 | signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); |
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| 74 | signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); |
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| 75 | signal sram : typ_dpram; |
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| 76 | |
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| 77 | signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); |
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| 78 | signal dpid,dpid_i : natural range 0 to 15:=DestId; |
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| 79 | signal MyRank :std_logic_vector(3 downto 0); |
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| 80 | signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque |
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| 81 | signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée |
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| 82 | signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO |
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| 83 | signal Lib_Init : std_logic; -- l'initialisation est terminée |
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| 84 | --signaux pour la gestion de la MAE |
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[39] | 85 | type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate, putdata,getdata,WinCompleted,finalize,st_timeout); |
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[15] | 86 | signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées |
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| 87 | signal count,count_i : natural range 0 to 15:=0; |
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| 88 | |
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| 89 | |
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| 90 | signal RunState : typ_mae; |
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| 91 | signal Ram_busy :std_logic:='0'; |
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| 92 | begin |
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| 93 | Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) |
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| 94 | PORT MAP( |
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| 95 | clka =>clk, |
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| 96 | clkb => clk, |
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| 97 | wea => ram_we, |
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| 98 | ena => ram_ena, |
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| 99 | enb => ram_enb, |
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| 100 | addra => ram_addra, |
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| 101 | addrb =>ram_addrb, |
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| 102 | dia => ram_din, |
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| 103 | dob => ram_do |
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| 104 | ); |
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| 105 | --================================================================ |
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| 106 | --MUX de la RAM |
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| 107 | |
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| 108 | Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr, |
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| 109 | Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do, |
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| 110 | Pe_ram_din,Pe_ram_we ) |
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| 111 | begin |
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| 112 | case ramsel is |
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| 113 | |
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| 114 | when '1' => |
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| 115 | ram_addra <= Core_ram_address_wr ; |
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| 116 | ram_addrb <= Core_ram_address_rd ; |
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| 117 | ram_ena <= Core_ram_en; |
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| 118 | ram_enb <= Core_ram_en; |
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| 119 | ram_we<= Core_ram_we; |
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| 120 | ram_din <= Core_ram_data_in; |
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| 121 | pe_ram_do<=(others=>'Z'); |
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| 122 | Core_ram_data_out<=ram_do; |
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| 123 | |
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| 124 | when others => |
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| 125 | ram_addra <= pe_ram_addra; |
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| 126 | ram_addrb <= pe_ram_addrb; |
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| 127 | ram_ena <= pe_ram_ena; |
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| 128 | ram_enb <= pe_ram_enb; |
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| 129 | ram_we<= pe_ram_we; |
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| 130 | ram_din <=pe_ram_din; |
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| 131 | Core_ram_data_out<=(others=>'Z'); |
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| 132 | pe_ram_do<=ram_do; |
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| 133 | end case ; |
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| 134 | end process ; |
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| 135 | |
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| 136 | |
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| 137 | |
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| 138 | Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --********A changer ********** |
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| 139 | --=== !!!!! attention la suppression de la ligne ci-dessous empêche ce |
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| 140 | -- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!! |
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| 141 | instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); |
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| 142 | |
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| 143 | dpid<=dpid_i; |
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| 144 | |
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| 145 | Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié |
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| 146 | Lib_init<=Core_Pushout(4); -- Initialized |
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| 147 | -- pe_hold_req<=Core_hold_req; |
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| 148 | --Core_hold_ack<=pe_hold_ack; |
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| 149 | |
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| 150 | hold:process (Core_Hold_Req,clk,reset) |
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| 151 | begin |
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| 152 | if rising_edge(clk) then |
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| 153 | if reset='1' then |
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| 154 | Core_Hold_Ack<='0'; |
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| 155 | else |
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| 156 | if Core_Hold_Req='1' then |
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| 157 | |
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| 158 | ramsel<=not(ram_busy); |
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| 159 | Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération |
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| 160 | Pe_hold_ack<=not(ram_busy); |
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| 161 | else |
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| 162 | Core_Hold_Ack<='0'; |
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| 163 | ramsel<='0'; |
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| 164 | Pe_hold_ack<='0'; |
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| 165 | |
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| 166 | end if; |
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| 167 | end if; |
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| 168 | end if; |
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| 169 | end process hold; |
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| 170 | --======================================================================= |
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| 171 | |
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| 172 | |
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| 173 | |
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| 174 | --======================================================================= |
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| 175 | --MAE du PE |
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| 176 | --======================================================================= |
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| 177 | |
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| 178 | pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do) |
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| 179 | |
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| 180 | constant DATAPTR : natural :=256; |
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| 181 | variable bfill,destrank,pid,mport : natural range 0 to 15; |
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| 182 | variable fsrc,ret : natural range 0 to 15:=0; |
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| 183 | variable timeout,ct,dlen : natural range 0 to 255; |
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| 184 | variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); |
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[39] | 185 | variable mywin : Mpi_win; |
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[15] | 186 | variable iack : std_logic:='0'; |
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| 187 | variable adresse,adresse_rd :natural range 0 to 65536; |
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| 188 | variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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[39] | 189 | --======================================================= |
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| 190 | --variables pour la création du fichier de résultats |
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| 191 | type char_file is file of character; |
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| 192 | file f: text; |
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| 193 | variable status :file_open_status ; |
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| 194 | variable char_count: integer range 0 to 65536 := 0; |
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| 195 | variable str: string (1 to 79) ; |
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| 196 | variable L: line; |
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| 197 | variable fopened: std_logic:='0'; |
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| 198 | --====================================================== |
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[15] | 199 | begin |
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| 200 | --=== Partie combinatoire du process =================================== |
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| 201 | Libr.Instr_ack<=Core_pushout(0); |
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| 202 | Libr.InitOk<=Core_pushout(4); |
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| 203 | Libr.Hold_Req<=Core_Hold_req; |
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| 204 | Libr.Hold_Ack<=Pe_Hold_Ack; |
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| 205 | Libr.RamSel<=RamSel; |
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| 206 | sram.data_out<=PE_ram_do; |
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[39] | 207 | --=== Fin de la partie combinatoire du process ========================== |
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| 208 | |
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| 209 | |
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| 210 | |
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| 211 | --end loop; |
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| 212 | |
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[15] | 213 | if (clk'event and clk='1') then |
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| 214 | if reset='1' then |
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| 215 | RunState<=start; |
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| 216 | |
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| 217 | else |
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| 218 | |
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| 219 | Libr.Instr_ack<=Core_pushout(0); |
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| 220 | Libr.InitOk<=Core_pushout(4); |
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| 221 | Libr.Hold_Req<=Core_Hold_req; |
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| 222 | Libr.Hold_Ack<=Pe_Hold_Ack; |
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| 223 | Libr.RamSel<=RamSel; |
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| 224 | sram.data_out<=PE_ram_do; |
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| 225 | case RunState is |
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| 226 | when start => |
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| 227 | Dcount<=0; |
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| 228 | if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide |
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| 229 | RunState<=Fillmem; |
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| 230 | end if; |
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| 231 | Ram_busy<='0'; |
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| 232 | PE_Instr_En<='0'; |
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| 233 | iack:='0'; |
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| 234 | adresse:=DATAPTR; |
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| 235 | |
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| 236 | adresse_rd:=0; |
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| 237 | timeout:=0; |
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| 238 | dcount<=0; |
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[39] | 239 | if fopened='0' then |
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| 240 | file_open(status,f, integer'image(destid) & "test_file0.txt", APPEND_MODE); |
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| 241 | --while not endfile(c_file_handle) loop |
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| 242 | --end if; |
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| 243 | |
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| 244 | --write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now))); |
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| 245 | --report l.all; |
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| 246 | -- writeline (f, l) ; |
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| 247 | fopened:='1'; |
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| 248 | end if; |
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| 249 | |
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[15] | 250 | when Fillmem => |
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| 251 | if Ramsel='0' then |
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| 252 | |
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| 253 | |
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| 254 | |
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| 255 | PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; |
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| 256 | PE_Instr_En<='0'; |
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| 257 | dcount<=dcount+1; |
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| 258 | |
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[35] | 259 | if dcount=200 then |
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[15] | 260 | bfill:=bfill+1; |
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| 261 | |
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| 262 | if bfill=4 then |
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| 263 | RunState<=InitApp; |
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| 264 | else |
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| 265 | RunState<=nextfill; |
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| 266 | end if; |
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| 267 | else |
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| 268 | adresse:=adresse+1; |
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| 269 | RunState<=Fillmem; |
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| 270 | end if; |
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| 271 | else -- attente de la libéraion de la mémoire |
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| 272 | timeout:=timeout+1; |
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| 273 | if timeout=100 then |
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| 274 | RunState<=st_timeout; |
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| 275 | end if; |
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| 276 | |
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| 277 | end if; |
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| 278 | when nextfill => --prépare le prochain bloc mémoire qui sera rempli |
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[35] | 279 | adresse:=200*bfill; |
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[15] | 280 | dcount<=0; |
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| 281 | ct:=0; |
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| 282 | RunState<=Fillmem; |
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| 283 | PE_Instr_En<='0'; |
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| 284 | when InitApp => |
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| 285 | --code pour Init |
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[39] | 286 | dlen:=1; |
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| 287 | if ct=0 then |
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| 288 | write (l,string'("Dlen; ;INIT of Process n°; " & image(MyRank) & "; started at ; " & time'image(now))); |
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| 289 | |
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| 290 | report l.all; |
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| 291 | writeline (f, l) ; |
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| 292 | end if; |
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[15] | 293 | pMPI_Init(ct,Libr,Clk,SRam); |
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| 294 | PE_Instr_EN<=Libr.instr_en; |
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| 295 | adresse:=to_integer(unsigned(sram.addr_wr)); |
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| 296 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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| 297 | PE_ram_din<=sram.data_in; |
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| 298 | |
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| 299 | --if Libr.InitOk='1' then |
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| 300 | if ct=0 then |
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[39] | 301 | RunState<=GetRank; |
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| 302 | write (l,string'("Dlen; ;INIT;" & "; ended at ; " & time'image(now))); |
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| 303 | report l.all; |
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| 304 | writeline (f, l) ; |
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[15] | 305 | end if; |
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| 306 | |
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| 307 | |
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| 308 | |
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[39] | 309 | when GetRank => |
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| 310 | if ct=0 then |
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[15] | 311 | |
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[39] | 312 | write (l,string'("Dlen; ; Rank ; " & "; started ; " & time'image(now))); |
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| 313 | report l.all; |
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| 314 | writeline (f, l) ; |
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| 315 | end if; |
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[15] | 316 | pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); |
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[39] | 317 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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[15] | 318 | if ct=0 then |
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[39] | 319 | RunState<=PutData; |
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| 320 | write (l,string'("Dlen; ; Rank ; " & "; ended at ; " & time'image(now))); |
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| 321 | report l.all; |
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| 322 | writeline (f, l) ; |
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[15] | 323 | end if; |
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[39] | 324 | |
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[15] | 325 | |
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[39] | 326 | when Wincreate => |
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| 327 | |
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| 328 | |
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[15] | 329 | when putdata => --construire le packet pour le Put |
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| 330 | |
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[39] | 331 | --dlen:=251; --- |
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| 332 | if ct=0 then |
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| 333 | write (l,string'("Dlen;" & integer'image(dlen) & ";Put of Pr n°; " & image(MyRank) & "; started at ; " & time'image(now))); |
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| 334 | report l.all; |
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| 335 | writeline (f, l) ; |
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| 336 | end if; |
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[15] | 337 | if unsigned(MyRank) = 0 then |
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| 338 | Destrank:=1; |
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| 339 | else |
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| 340 | DestRank:=0; |
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| 341 | end if; |
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[39] | 342 | |
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[15] | 343 | SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); |
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| 344 | DestAdr:=X"2000"; |
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| 345 | |
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[39] | 346 | pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); |
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[15] | 347 | adresse:=to_integer(unsigned(sram.addr_wr)); |
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| 348 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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| 349 | PE_Instr_EN<=Libr.instr_en; |
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| 350 | PE_ram_din<=sram.data_in; |
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| 351 | dcount<=ct; |
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| 352 | |
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| 353 | if ct=0 then |
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| 354 | RunState<=GetData; |
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[39] | 355 | report "Put of Process n°; " & image(MyRank) & "; ended at ; " & time'image(now); |
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| 356 | write (l,string'("Dlen;" & integer'image(dlen) & ";Put of Pr n°; " & image(MyRank) & "; ended at time ; " & time'image(now))); |
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| 357 | report l.all; |
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| 358 | writeline (f, l) ; |
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[15] | 359 | end if; |
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[39] | 360 | |
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[15] | 361 | |
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| 362 | when getdata => --positionnement du mot de longueur des données |
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[39] | 363 | --dlen:=251; --- |
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| 364 | if ct=0 then |
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| 365 | write (l,string'("Dlen;" & integer'image(dlen) & ";GET of Process n°; " & image(MyRank) & "; started at ; " & time'image(now))); |
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| 366 | report l.all; |
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| 367 | writeline (f, l) ; |
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| 368 | end if; |
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| 369 | |
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[35] | 370 | SrcAdr:=X"0120"; |
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| 371 | DestAdr:=X"4000"; |
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[15] | 372 | |
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[39] | 373 | pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); |
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[15] | 374 | adresse:=to_integer(unsigned(sram.addr_wr)); |
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| 375 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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| 376 | PE_Instr_EN<=Libr.instr_en; |
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| 377 | PE_ram_din<=sram.data_in; |
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| 378 | dcount<=ct; |
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| 379 | |
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| 380 | if ct=0 then |
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[39] | 381 | RunState<=wincompleted; |
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| 382 | assert ct/=0 report "GET_END " & integer'image(destrank) |
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| 383 | severity Warning ; |
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| 384 | write (l,string'("Dlen ;" & integer'image(dlen) & ";GET of Proc n°; " & image(MyRank) & "; ended at ; " & time'image(now))); |
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| 385 | report l.all; |
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| 386 | |
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| 387 | writeline (f, l) ; |
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[15] | 388 | end if; |
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| 389 | |
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[39] | 390 | when WinCompleted => |
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| 391 | if ct=0 then |
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| 392 | write (l,string'("Dlen ;" & integer'image(dlen) & ";Wait of Proc n°; " & image(MyRank) & "; started at ; " & time'image(now))); |
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| 393 | report l.all; |
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| 394 | writeline (f, l) ; |
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| 395 | end if; |
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| 396 | pMPI_Win_wait(ct,Libr,sram,MyWin ); |
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| 397 | adresse:=to_integer(unsigned(sram.addr_wr)); |
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| 398 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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| 399 | if ct=0 then |
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| 400 | RunState<=finalize; |
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| 401 | write (l,string'("Dlen ;" & integer'image(dlen) & ";Wait of Proc n°; " & image(MyRank) & "; ended at ; " & time'image(now))); |
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| 402 | report l.all; |
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| 403 | writeline (f, l) ; |
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| 404 | |
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| 405 | end if; |
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[15] | 406 | |
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| 407 | |
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[39] | 408 | when finalize => |
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| 409 | if ct=0 then |
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| 410 | write (l,string'("Dlen ;" & integer'image(dlen) & ";Finalize of Proc n°; " & image(MyRank) & "; started at ; " & time'image(now))); |
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| 411 | report l.all; |
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| 412 | writeline (f, l) ; |
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| 413 | end if; |
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| 414 | |
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| 415 | if ct=0 then |
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| 416 | RunState<=start; |
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| 417 | write (l,string'("Dlen ;" & integer'image(dlen) & ";Finalize of Proc n°; " & image(MyRank) & "; ended at ; " & time'image(now))); |
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| 418 | report l.all; |
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| 419 | writeline (f, l) ; |
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| 420 | file_close(f); |
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| 421 | end if; |
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[15] | 422 | |
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| 423 | when st_timeout => |
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| 424 | |
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| 425 | --if ram_busy='1' then |
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| 426 | RunState<=start; |
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| 427 | --end if |
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| 428 | |
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| 429 | RunState<=start; |
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| 430 | end case; |
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| 431 | pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16)); |
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| 432 | pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16)); |
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| 433 | end if; |
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| 434 | end if; |
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| 435 | |
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| 436 | end process pPutGet; |
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| 437 | |
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| 438 | majPutGet:process (RunState,pe_ram_do,sram,Lib_Init) |
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| 439 | |
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| 440 | begin |
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| 441 | case RunState is |
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| 442 | when start => |
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| 443 | |
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| 444 | PE_Ram_we<='0'; |
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| 445 | PE_Ram_ena<='0'; |
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| 446 | PE_Ram_enb<='0'; |
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| 447 | --PE_Instr_En<='0'; |
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| 448 | |
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| 449 | when fillmem => |
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| 450 | PE_Ram_we<='1'; |
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| 451 | PE_Ram_ena<='1'; |
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| 452 | |
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| 453 | PE_Ram_enb<='0'; |
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| 454 | --PE_Instr_En<='0'; |
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| 455 | when nextfill => |
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| 456 | PE_Ram_we<='1'; |
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| 457 | PE_Ram_ena<='1'; |
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| 458 | PE_Ram_enb<='0'; |
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| 459 | |
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| 460 | when InitApp => |
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| 461 | -- PE_Ram_we<='1'; |
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| 462 | -- PE_Ram_ena<='1'; |
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| 463 | -- PE_Ram_enb<='0'; |
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| 464 | PE_Ram_we<=sram.we; |
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| 465 | PE_Ram_ena<=sram.ena; |
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| 466 | PE_Ram_enb<=sram.enb; |
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| 467 | |
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[39] | 468 | |
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| 469 | when GetRank => |
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[15] | 470 | |
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| 471 | PE_Ram_we<=sram.we; |
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| 472 | PE_Ram_ena<=sram.ena; |
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| 473 | PE_Ram_enb<=sram.enb; |
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[39] | 474 | when WinCreate => |
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[15] | 475 | |
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[39] | 476 | PE_Ram_we<=sram.we; |
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| 477 | PE_Ram_ena<=sram.ena; |
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| 478 | PE_Ram_enb<=sram.enb; |
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[15] | 479 | |
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| 480 | |
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[39] | 481 | --positionnement du mot de longueur des données |
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[15] | 482 | |
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| 483 | |
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[39] | 484 | when putdata => |
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[15] | 485 | srcadr0<=X"00"; |
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| 486 | srcadr1<=X"01"; |
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| 487 | destadr0<=X"00"; |
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| 488 | destadr1<=X"02"; |
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| 489 | PE_Ram_we<=sram.we; |
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| 490 | PE_Ram_ena<=sram.ena; |
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| 491 | PE_Ram_enb<=sram.enb; |
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[39] | 492 | |
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[15] | 493 | when getdata => |
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| 494 | PE_Ram_we<=sram.we; |
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| 495 | PE_Ram_ena<=sram.ena; |
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| 496 | PE_Ram_enb<=sram.enb; |
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| 497 | |
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[39] | 498 | when Wincompleted => |
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| 499 | PE_Ram_we<=sram.we; |
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| 500 | PE_Ram_ena<=sram.ena; |
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| 501 | PE_Ram_enb<=sram.enb; |
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[15] | 502 | |
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[39] | 503 | when finalize => |
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[15] | 504 | |
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| 505 | PE_Ram_we<='0'; |
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| 506 | PE_Ram_ena<='0'; |
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| 507 | PE_Ram_enb<='0'; |
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| 508 | |
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| 509 | |
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| 510 | when st_timeout => |
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| 511 | PE_Ram_we<='0'; |
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| 512 | PE_Ram_ena<='0'; |
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| 513 | PE_Ram_enb<='0'; |
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| 514 | |
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| 515 | |
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| 516 | end case; |
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| 517 | |
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| 518 | end process majPutGet ; |
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| 519 | end Behavioral; |
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| 520 | |
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